Build starting @ 2019-03-05T02:46:38.574350 Running make -C /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid run (with MAKEFLAGS=' -j --jobserver-fds=3,4') --------------------------------------------------------------------------- make[1]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' make clean make[2]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' rm -rf build run.ok cd clb && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' cd clb_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' cd iob && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' cd iob_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' cd mmcm && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/mmcm' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/mmcm' cd pll && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/pll' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/pll' cd ps7_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/ps7_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/ps7_int' cd bram && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' cd bram_block && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' cd bram_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' cd dsp && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' cd dsp_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp_int' cd fifo_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' cd monitor && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' cd monitor_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' cd cfg_int && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' cd orphan_int_column && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/orphan_int_column' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/orphan_int_column' cd clk_hrow && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_hrow' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_hrow' cd clk_bufg && make clean make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_bufg' rm -rf build make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clk_bufg' make[2]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' make database make[2]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' bash generate.sh build/tiles tiles ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/generate_tiles.tcl # source "$::env(FUZDIR)/util.tcl" ## proc min_ysite { duts_in_column } { ## # Given a list of sites, return the one with the lowest Y coordinate ## ## set min_dut_y 9999999 ## ## foreach dut $duts_in_column { ## # Ex: SLICE_X2Y50/A6LUT ## # Ex: IOB_X1Y50 ## regexp ".*_X([0-9]+)Y([0-9]+)" $dut match dut_x dut_y ## ## if { $dut_y < $min_dut_y } { ## set selected_dut $dut ## set min_dut_y $dut_y ## } ## } ## return $selected_dut ## } ## proc group_dut_cols { duts ypitch } { ## # Group a list of sites into pitch sized buckets ## # Ex: IOBs occur 75 to a CMT column ## # Set pitch to 75 to get 0-74 in one bucket, 75-149 in a second, etc ## # X0Y0 {IOB_X0Y49 IOB_X0Y48 IOB_X0Y47 ... } ## # Anything with a different x is automatically in a different bucket ## ## # LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per CMT column) ## set dut_columns "" ## foreach dut $duts { ## # Ex: SLICE_X2Y50/A6LUT ## # Ex: IOB_X1Y50 ## regexp ".*_X([0-9]+)Y([0-9]+)" $dut match dut_x dut_y ## ## # 75 per column => 0, 75, 150, etc ## set y_column [expr ($dut_y / $ypitch) * $ypitch] ## dict append dut_columns "X${dut_x}Y${y_column}" "$dut " ## } ## return $dut_columns ## } ## proc loc_dut_col_bels { dut_columns cellpre cellpost } { ## # set cellpre di ## ## # Pick the smallest Y in each column and LOC a cell to it ## # cells must be named like $cellpre[$dut_index] ## # Return the selected sites ## ## set ret_bels {} ## set dut_index 0 ## ## dict for {column duts_in_column} $dut_columns { ## set sel_bel_str [min_ysite $duts_in_column] ## set sel_bel [get_bels $sel_bel_str] ## if {"$sel_bel" == ""} {error "Bad bel $sel_bel from bel str $sel_bel_str"} ## set sel_site [get_sites -of_objects $sel_bel] ## if {"$sel_site" == ""} {error "Bad site $sel_site from bel $sel_bel"} ## ## set cell [get_cells $cellpre$dut_index$cellpost] ## puts "LOCing cell $cell to site $sel_site (from bel $sel_bel)" ## set_property LOC $sel_site $cell ## ## set dut_index [expr $dut_index + 1] ## lappend ret_bels $sel_bel ## } ## ## return $ret_bels ## } ## proc loc_dut_col_sites { dut_columns cellpre cellpost } { ## set bels [loc_dut_col_bels $dut_columns $cellpre $cellpost] ## set sites [get_sites -of_objects $bels] ## return $sites ## } ## proc make_io_pad_sites {} { ## # get all possible IOB pins ## foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { ## set site [get_sites -of_objects $pad] ## if {[llength $site] == 0} { ## continue ## } ## if [string match IOB33* [get_property SITE_TYPE $site]] { ## dict append io_pad_sites $site $pad ## } ## } ## return $io_pad_sites ## } ## proc make_iob_pads {} { ## set io_pad_sites [make_io_pad_sites] ## ## set iopad "" ## dict for {key value} $io_pad_sites { ## # Some sites have more than one pad? ## lappend iopad [lindex $value 0] ## } ## return $iopad ## } ## proc make_iob_sites {} { ## set io_pad_sites [make_io_pad_sites] ## ## set sites "" ## dict for {key value} $io_pad_sites { ## lappend sites $key ## } ## return $sites ## } ## proc assign_iobs_old {} { ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] ## set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] ## } ## proc assign_iobs {} { ## # Set all I/Os on the bus to valid values somewhere on the chip ## # The iob fuzzer sets these to more specific values ## ## # All possible IOs ## set iopad [make_iob_pads] ## # Basic pins ## # XXX: not all pads are valid, but seems to be working for now ## # Maybe better to set to XRAY_PIN_* and take out of the list? ## set_property -dict "PACKAGE_PIN [lindex $iopad 0] IOSTANDARD LVCMOS33" [get_ports clk] ## set_property -dict "PACKAGE_PIN [lindex $iopad 1] IOSTANDARD LVCMOS33" [get_ports do] ## set_property -dict "PACKAGE_PIN [lindex $iopad 2] IOSTANDARD LVCMOS33" [get_ports stb] ## ## # din bus ## set fixed_pins 3 ## set iports [get_ports di*] ## for {set i 0} {$i < [llength $iports]} {incr i} { ## set pad [lindex $iopad [expr $i+$fixed_pins]] ## set port [lindex $iports $i] ## set_property -dict "PACKAGE_PIN $pad IOSTANDARD LVCMOS33" $port ## } ## } ## proc make_project {} { ## # Generate .bit only over ROI ## make_project_roi XRAY_ROI_TILEGRID ## } ## proc make_project_roi { roi_var } { ## # 6 CMTs in our reference part ## # What is the largest? ## set n_di 16 ## ## create_project -force -part $::env(XRAY_PART) design design ## ## read_verilog "$::env(FUZDIR)/top.v" ## synth_design -top top -verilog_define N_DI=$n_di ## ## assign_iobs ## ## create_pblock roi ## add_cells_to_pblock [get_pblocks roi] [get_cells roi] ## foreach roi "$::env($roi_var)" { ## puts "ROI: $roi" ## resize_pblock [get_pblocks roi] -add "$roi" ## } ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## set_param tcl.collectionResultDisplayLimit 0 ## ## set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] ## } # proc write_tiles_txt {} { # # Get all tiles, ie not just the selected LUTs # set tiles [get_tiles] # # # Write tiles.txt with site metadata # set fp [open "tiles.txt" w] # foreach tile $tiles { # set type [get_property TYPE $tile] # set grid_x [get_property GRID_POINT_X $tile] # set grid_y [get_property GRID_POINT_Y $tile] # set sites [get_sites -quiet -of_objects $tile] # set typed_sites {} # # if [llength $sites] { # set site_types [get_property SITE_TYPE $sites] # foreach t $site_types s $sites { # lappend typed_sites $t $s # } # } # # puts $fp "$type $tile $grid_x $grid_y $typed_sites" # } # close $fp # } # proc run {} { # # Generate grid of entire part # make_project_roi XRAY_ROI_TILEGRID # # place_design # route_design # write_checkpoint -force design.dcp # write_bitstream -force design.bit # # write_tiles_txt # } # run Command: synth_design -top top -verilog_define N_DI=16 Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 2718 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 29232 ; free virtual = 55163 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:14] Parameter DIN_N bound to: 16 - type: integer Parameter DOUT_N bound to: 108 - type: integer INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUF' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] INFO: [Synth 8-638] synthesizing module 'roi' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:50] INFO: [Synth 8-638] synthesizing module 'LUT6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized0' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized1' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized2' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized3' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized3' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized4' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized5' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized5' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized6' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized7' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized7' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized8' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized9' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized9' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized10' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized10' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized11' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized11' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized12' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized12' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized13' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized13' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized14' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized14' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized15' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized15' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized16' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized16' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized17' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized17' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized18' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized18' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized19' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized19' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized20' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized20' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized21' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized21' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized22' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized22' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized23' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized23' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized24' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized24' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized25' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized25' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized26' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized26' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized27' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized27' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized28' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized28' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized29' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized29' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized30' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000000111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized30' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized31' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized31' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized32' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized32' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized33' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized33' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized34' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized34' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized35' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized35' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized36' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized36' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized37' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized37' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized38' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized38' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized39' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized39' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized40' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized40' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized41' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized41' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized42' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized42' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized43' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized43' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized44' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized44' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized45' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized45' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized46' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized46' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized47' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized47' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized48' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized48' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized49' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized49' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized50' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized50' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized51' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized51' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized52' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized52' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized53' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized53' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized54' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized54' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized55' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized55' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized56' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized56' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized57' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized57' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized58' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized58' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized59' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized59' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized60' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized60' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized61' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized61' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized62' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000001111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized62' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized63' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized63' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized64' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized64' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized65' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized65' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized66' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized66' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized67' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized67' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized68' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized68' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized69' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized69' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized70' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010001110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized70' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized71' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized71' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized72' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized72' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized73' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized73' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized74' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010010110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized74' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized75' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized75' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized76' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized76' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized77' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized77' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized78' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010011110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized78' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized79' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized79' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized80' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized80' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized81' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized81' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized82' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010100110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized82' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized83' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized83' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized84' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized84' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized85' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized85' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized86' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010101110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized86' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized87' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized87' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized88' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized88' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized89' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized89' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized90' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010110110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized90' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized91' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized91' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized92' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized92' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized93' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized93' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized94' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000010111110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized94' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized95' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000000000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized95' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized96' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000010000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized96' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized97' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000100000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized97' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'LUT6__parameterized98' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b1000000000000000000000000000000000000000011000110000000000000001 INFO: [Synth 8-256] done synthesizing module 'LUT6__parameterized98' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] INFO: [Synth 8-638] synthesizing module 'RAMB36E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized0' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized0' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized1' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized2' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized2' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized3' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized3' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized3' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized4' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized4' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized5' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized5' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized5' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-638] synthesizing module 'RAMB36E1__parameterized6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter EN_ECC_READ bound to: FALSE - type: string Parameter EN_ECC_WRITE bound to: FALSE - type: string Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_40 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_41 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_42 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_43 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_44 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_45 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_46 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_47 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_48 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_49 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_4F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_50 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_51 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_52 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_53 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_54 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_55 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_56 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_57 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_58 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_59 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_5F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_60 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_61 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_62 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_63 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_64 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_65 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_66 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_67 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_68 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_69 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_6F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_70 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_71 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_72 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_73 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_74 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_75 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_76 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_77 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_78 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_79 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_7F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 36'b000000000000000000000000000000000000 Parameter INIT_B bound to: 36'b000000000000000000000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_EXTENSION_A bound to: NONE - type: string Parameter RAM_EXTENSION_B bound to: NONE - type: string Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 36'b000000000000000000000000000000000000 Parameter SRVAL_B bound to: 36'b000000000000000000000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB36E1__parameterized6' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:42488] WARNING: [Synth 8-689] width (1) of port connection 'ADDRARDADDR' does not match port width (16) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:85] WARNING: [Synth 8-689] width (1) of port connection 'ADDRBWRADDR' does not match port width (16) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:86] WARNING: [Synth 8-689] width (1) of port connection 'DIADI' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:87] WARNING: [Synth 8-689] width (1) of port connection 'DIBDI' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:88] WARNING: [Synth 8-689] width (1) of port connection 'DIPADIP' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:89] WARNING: [Synth 8-689] width (1) of port connection 'DIPBDIP' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:90] WARNING: [Synth 8-689] width (1) of port connection 'WEA' does not match port width (4) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:91] WARNING: [Synth 8-689] width (1) of port connection 'WEBWE' does not match port width (8) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:92] WARNING: [Synth 8-689] width (1) of port connection 'DOADO' does not match port width (32) of module 'RAMB36E1__parameterized6' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:93] WARNING: [Synth 8-350] instance 'bram' of module 'RAMB36E1' requires 32 connections, but only 22 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:74] INFO: [Synth 8-256] done synthesizing module 'roi' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:50] INFO: [Synth 8-256] done synthesizing module 'top' (5#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:14] WARNING: [Synth 8-3331] design roi has unconnected port clk --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 29240 ; free virtual = 55172 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 29243 ; free virtual = 55175 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 29243 ; free virtual = 55175 --------------------------------------------------------------------------------- WARNING: [Synth 8-3936] Found unconnected internal register 'din_reg' and it is trimmed from '16' to '8' bits. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/top.v:36] INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1205.953 ; gain = 110.508 ; free physical = 29236 ; free virtual = 55168 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 108 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 1 +---Muxes : 2 Input 108 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 108 Bit Registers := 1 16 Bit Registers := 1 8 Bit Registers := 1 +---Muxes : 2 Input 108 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3332] Sequential element (di_bufs[8].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[9].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[10].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[11].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[12].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[13].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (di_bufs[14].ibuf) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[14]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[13]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[12]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[11]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[10]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[9]) is unused and will be removed from module top. WARNING: [Synth 8-3332] Sequential element (din_shr_reg[8]) is unused and will be removed from module top. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1328.922 ; gain = 233.477 ; free physical = 29036 ; free virtual = 54968 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1328.922 ; gain = 233.477 ; free physical = 29036 ; free virtual = 54967 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 29034 ; free virtual = 54966 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 29034 ; free virtual = 54966 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 29034 ; free virtual = 54966 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 29034 ; free virtual = 54966 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 29034 ; free virtual = 54966 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 29034 ; free virtual = 54966 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 29034 ; free virtual = 54966 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 3| |2 |LUT3 | 108| |3 |LUT6 | 100| |4 |RAMB36E1 | 8| |5 |FDRE | 125| |6 |IBUF | 11| |7 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 356| |2 | roi |roi | 216| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 29034 ; free virtual = 54966 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 96 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.938 ; gain = 243.492 ; free physical = 29035 ; free virtual = 54967 Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1338.945 ; gain = 243.492 ; free physical = 29037 ; free virtual = 54969 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 19 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 230 Infos, 96 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1472.965 ; gain = 390.074 ; free physical = 28976 ; free virtual = 54908 ROI: SLICE_X0Y0:SLICE_X43Y99 ROI: RAMB18_X0Y0:RAMB18_X2Y39 ROI: RAMB36_X0Y0:RAMB36_X2Y19 ROI: DSP48_X0Y0:DSP48_X1Y39 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1536.996 ; gain = 0.000 ; free physical = 28969 ; free virtual = 54901 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 17075422c Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1536.996 ; gain = 0.000 ; free physical = 28969 ; free virtual = 54901 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1922.484 ; gain = 0.000 ; free physical = 28645 ; free virtual = 54577 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y37 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 196761f3e Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.500 ; gain = 417.504 ; free physical = 28643 ; free virtual = 54575 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.500 ; gain = 417.504 ; free physical = 28643 ; free virtual = 54575 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.500 ; gain = 417.504 ; free physical = 28643 ; free virtual = 54575 Phase 1 Placer Initialization | Checksum: 1e62e4f20 Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1954.500 ; gain = 417.504 ; free physical = 28643 ; free virtual = 54575 Phase 2 Global Placement WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 22c942a2c Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28587 ; free virtual = 54519 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 22c942a2c Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28587 ; free virtual = 54519 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18f2ccf33 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28587 ; free virtual = 54519 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 18d8a98aa Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28587 ; free virtual = 54519 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 18d8a98aa Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28587 ; free virtual = 54519 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28583 ; free virtual = 54515 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28583 ; free virtual = 54515 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28583 ; free virtual = 54515 Phase 3 Detail Placement | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28583 ; free virtual = 54515 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28583 ; free virtual = 54515 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28585 ; free virtual = 54517 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21d012c21 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28585 ; free virtual = 54517 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1ce33f28d Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28585 ; free virtual = 54517 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1ce33f28d Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28585 ; free virtual = 54517 Ending Placer Task | Checksum: 14c774d33 Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 2042.543 ; gain = 505.547 ; free physical = 28598 ; free virtual = 54530 240 Infos, 98 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:12 . Memory (MB): peak = 2042.543 ; gain = 569.578 ; free physical = 28598 ; free virtual = 54530 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y37 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9c4f4a11 ConstDB: 0 ShapeSum: b0280322 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: f8e08080 Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 2072.188 ; gain = 29.645 ; free physical = 28579 ; free virtual = 54511 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f8e08080 Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 2079.176 ; gain = 36.633 ; free physical = 28547 ; free virtual = 54479 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f8e08080 Time (s): cpu = 00:00:22 ; elapsed = 00:00:18 . Memory (MB): peak = 2079.176 ; gain = 36.633 ; free physical = 28547 ; free virtual = 54479 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b8accb7e Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2094.230 ; gain = 51.688 ; free physical = 28537 ; free virtual = 54469 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: fc55de3b Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 2094.230 ; gain = 51.688 ; free physical = 28542 ; free virtual = 54474 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 31 Number of Nodes with overlaps = 0 Phase 4.1 Global Iteration 0 | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 2094.230 ; gain = 51.688 ; free physical = 28580 ; free virtual = 54512 Phase 4 Rip-up And Reroute | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 2094.230 ; gain = 51.688 ; free physical = 28580 ; free virtual = 54512 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 2094.230 ; gain = 51.688 ; free physical = 28580 ; free virtual = 54512 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 2094.230 ; gain = 51.688 ; free physical = 28580 ; free virtual = 54512 Phase 6 Post Hold Fix | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 2094.230 ; gain = 51.688 ; free physical = 28580 ; free virtual = 54512 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.0324117 % Global Horizontal Routing Utilization = 0.0410751 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. East Dir 1x1 Area, Max Cong = 20.5882%, No Congested Regions. West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions. Phase 7 Route finalize | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 2094.230 ; gain = 51.688 ; free physical = 28580 ; free virtual = 54512 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 2094.230 ; gain = 51.688 ; free physical = 28579 ; free virtual = 54510 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1323db277 Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 2094.230 ; gain = 51.688 ; free physical = 28579 ; free virtual = 54510 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 2094.230 ; gain = 51.688 ; free physical = 28612 ; free virtual = 54544 Routing Is Done. 247 Infos, 99 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:20 . Memory (MB): peak = 2133.020 ; gain = 90.477 ; free physical = 28612 ; free virtual = 54544 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2133.020 ; gain = 0.000 ; free physical = 28611 ; free virtual = 54545 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:47:49 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 257 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 2474.125 ; gain = 341.105 ; free physical = 28527 ; free virtual = 54463 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:47:56 2019... mkdir -p build/basicdb cd build && python3 /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/generate.py \ --tiles /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/tiles/tiles.txt \ --out /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/build/basicdb/tilegrid.json cd iob && make cd iob_int && make cd monitor && make cd bram && make cd bram_block && make cd bram_int && make cd clb && make cd clb_int && make cd dsp && make cd fifo_int && make cd cfg_int && make cd monitor_int && make make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb' GENERATE_ARGS="--oneval 1 --design params.csv --dframe 26 --dword 1" bash ../fuzzaddr/generate.sh build/specimen_001 make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' GENERATE_ARGS="--oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24" bash ../fuzzaddr/generate.sh build/specimen_001 make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_001 make[3]: Entering directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' GENERATE_ARGS="--oneval 0 --design params.csv --dframe 14 --dword 1" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_001 GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_001 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc make_io_pin_sites {} { # # get all possible IOB pins # foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { # set site [get_sites -of_objects $pad] # if {[llength $site] == 0} { # continue # } # if [string match IOB33* [get_property SITE_TYPE $site]] { # dict append io_pin_sites $site $pad # } # } # return $io_pin_sites # } # proc load_pin_lines {} { # # IOB_X0Y103 clk input # # IOB_X0Y129 do[0] output # # set fp [open "params.csv" r] # gets $fp line # # set pin_lines {} # for {gets $fp line} {$line != ""} {gets $fp line} { # lappend pin_lines [split $line ","] # } # close $fp # return $pin_lines # } # proc loc_pins {} { # set pin_lines [load_pin_lines] # set io_pin_sites [make_io_pin_sites] # # puts "Looping" # for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { # set line [lindex $pin_lines $idx] # puts "$line" # # set site_str [lindex $line 2] # set pin_str [lindex $line 3] # # # Have: site # # Want: pin for site # # set site [get_sites $site_str] # set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}] # # set port [get_ports -of_objects $site] # set port [get_ports $pin_str] # set tile [get_tiles -of_objects $site] # # set pin [dict get $io_pin_sites $site] # set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port # } # } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # loc_pins # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } # run ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc make_io_pin_sites {} { # # get all possible IOB pins # foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { # set site [get_sites -of_objects $pad] # if {[llength $site] == 0} { # continue # } # if [string match IOB33* [get_property SITE_TYPE $site]] { # dict append io_pin_sites $site $pad # } # } # return $io_pin_sites # } # proc load_pin_lines {} { # # IOB_X0Y103 clk input # # IOB_X0Y129 do[0] output # # set fp [open "params.csv" r] # set pin_lines {} # for {gets $fp line} {$line != ""} {gets $fp line} { # lappend pin_lines [split $line ","] # } # close $fp # return $pin_lines # } # proc loc_pins {} { # set pin_lines [load_pin_lines] # set io_pin_sites [make_io_pin_sites] # # puts "Looping" # for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { # set line [lindex $pin_lines $idx] # puts "$line" # # set site_str [lindex $line 3] # set pin_str [lindex $line 4] # # # Have: site # # Want: pin for site # # set site [get_sites $site_str] # set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}] # # set port [get_ports -of_objects $site] # set port [get_ports $pin_str] # set tile [get_tiles -of_objects $site] # # set pin [dict get $io_pin_sites $site] # set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" $port # } # } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # loc_pins # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # run # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5061 INFO: Helper process launched with PID 5060 INFO: Helper process launched with PID 5062 INFO: Launching helper process for spawning children vivado processes Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Helper process launched with PID 5079 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5120 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Helper process launched with PID 5128 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5151 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5230 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5251 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5282 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5347 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5456 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 26885 ; free virtual = 52836 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 26878 ; free virtual = 52829 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 26866 ; free virtual = 52816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 26857 ; free virtual = 52807 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 26837 ; free virtual = 52787 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 26811 ; free virtual = 52761 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.434 ; gain = 60.824 ; free physical = 26800 ; free virtual = 52750 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 26794 ; free virtual = 52744 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.988 ; free physical = 26768 ; free virtual = 52718 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 26752 ; free virtual = 52702 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 26739 ; free virtual = 52690 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:1575] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/top.v:2] Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:238] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:258] Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 26631 ; free virtual = 52583 --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:263] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:273] Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 26631 ; free virtual = 52582 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:278] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:428] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:433] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:453] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:453] Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:458] Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:458] Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:463] Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:463] Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:468] Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:468] Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:473] Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:473] Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:478] Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:478] Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:483] Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:483] Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:488] Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:488] Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:493] Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:493] Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:498] Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/top.v:2] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:16] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 26589 ; free virtual = 52541 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 26590 ; free virtual = 52541 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 26590 ; free virtual = 52541 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 26587 ; free virtual = 52538 --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 --------------------------------------------------------------------------------- Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 26591 ; free virtual = 52542 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/top.v:2] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 26629 ; free virtual = 52581 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:4] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:9] INFO: [Synth 8-638] synthesizing module 'LUT6' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20668] WARNING: [Synth 8-350] instance 'dummy_lut' of module 'LUT6' requires 7 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:9] INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] INFO: [Synth 8-256] done synthesizing module 'top' (3#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/build/specimen_001/top.v:4] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 26655 ; free virtual = 52616 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 26659 ; free virtual = 52615 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 26667 ; free virtual = 52620 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:65] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:2] Parameter DIN_N bound to: 8 - type: integer WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:65] Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:25] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:85] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:85] Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:90] Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:90] Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:95] Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:95] Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:100] Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:185] INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:210] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:16] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:240] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:7] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:250] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/top.v:2] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 26696 ; free virtual = 52648 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 26696 ; free virtual = 52652 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 26697 ; free virtual = 52654 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 26698 ; free virtual = 52655 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:4] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'IDELAYCTRL' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16506] Parameter SIM_DEVICE bound to: 7SERIES - type: string Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 26695 ; free virtual = 52655 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'IDELAYCTRL' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16506] WARNING: [Synth 8-350] instance 'idelayctrl' of module 'IDELAYCTRL' requires 3 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:8] INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUF' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:14470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] INFO: [Synth 8-638] synthesizing module 'IDELAYE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16519] Parameter CINVCTRL_SEL bound to: FALSE - type: string Parameter DELAY_SRC bound to: IDATAIN - type: string Parameter HIGH_PERFORMANCE_MODE bound to: FALSE - type: string Parameter IDELAY_TYPE bound to: FIXED - type: string Parameter IDELAY_VALUE bound to: 0 - type: integer Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_DATAIN_INVERTED bound to: 1'b0 Parameter IS_IDATAIN_INVERTED bound to: 1'b0 Parameter PIPE_SEL bound to: FALSE - type: string Parameter REFCLK_FREQUENCY bound to: 200.000000 - type: float Parameter SIGNAL_PATTERN bound to: DATA - type: string Parameter SIM_DELAY_D bound to: 0 - type: integer --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'IDELAYE2' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16519] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y0' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y49' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 26699 ; free virtual = 52656 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:43] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y19' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:43] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:55] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y20' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y31' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y32' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y43' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y44' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:115] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y7' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:127] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y8' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:139] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y13' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:139] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:151] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y14' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:151] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:163] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y37' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 26706 ; free virtual = 52662 WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y38' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y1' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y2' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:211] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y11' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:223] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y12' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:235] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y15' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:247] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y16' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:259] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y17' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:271] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y18' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:271] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:283] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y21' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:295] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y22' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:307] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y23' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:319] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y24' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:319] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:331] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y25' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:343] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y26' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:355] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y27' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:367] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y28' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:367] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y29' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y30' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] No constraint files found. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y3' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y4' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y33' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y34' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] Detailed RTL Component Info : --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y35' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y36' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] --------------------------------------------------------------------------------- Start Part Resource Summary WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y39' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y40' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y41' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 26703 ; free virtual = 52656 WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y42' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y45' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y46' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y47' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y48' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] Loading part: xc7z020clg400-1 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:571] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y5' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:583] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y6' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:583] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:595] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y9' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:607] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X0Y10' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:607] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y0' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:631] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y100' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:643] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 26700 ; free virtual = 52653 WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y149' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y49' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:667] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y50' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:679] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y99' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:691] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y107' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:703] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y108' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:703] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:715] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y119' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:727] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y120' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:739] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y131' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:751] Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 26704 ; free virtual = 52657 WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y132' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:751] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:763] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y143' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:775] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y144' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:775] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y19' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y20' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y31' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y32' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y43' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y44' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:859] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y57' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:871] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y58' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:871] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:883] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y69' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:895] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y70' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y7' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y8' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:931] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y81' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:943] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y82' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:943] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:955] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y93' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:967] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y94' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:967] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:979] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y113' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:991] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y114' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:991] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y13' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y14' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y137' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1039] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y138' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1039] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y37' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y38' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y63' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1087] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y64' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1087] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y87' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1111] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y88' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y1' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y2' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y101' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1159] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y102' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1159] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y103' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1183] WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y104' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1195] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'idelay_IDELAY_X1Y105' of module 'IDELAYE2' requires 12 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1195] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 26697 ; free virtual = 52650 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 26697 ; free virtual = 52650 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 26696 ; free virtual = 52649 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:146] Report RTL Partitions: WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:164] +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:478] No constraint files found. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:618] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:644] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:2] Detailed RTL Component Info : WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:8] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:662] --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:727] Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:745] Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:784] Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer --------------------------------------------------------------------------------- Parameter DREG bound to: 1 - type: integer Start Part Resource Summary --------------------------------------------------------------------------------- Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:810] Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:828] Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1806] INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1863] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1889] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:15] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1946] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1990] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2055] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:36] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2112] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2138] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:43] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2221] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:57] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2304] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:64] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2387] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:78] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2405] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:92] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2527] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2553] Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 26697 ; free virtual = 52649 INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2571] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2636] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:113] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2654] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2719] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:127] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2776] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2802] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:141] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2859] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2885] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2942] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:162] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2986] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3051] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:176] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3108] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:190] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3191] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3235] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3300] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:211] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3357] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3383] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3440] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3549] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:246] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3606] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3632] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:260] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3689] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3733] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3798] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:281] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3816] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3881] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:295] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3938] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3964] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4021] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4047] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:316] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4065] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:330] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:344] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4231] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:351] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4314] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:365] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4397] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:372] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:386] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4563] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:393] No constraint files found. WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4646] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:407] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4729] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:421] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4812] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:428] Detailed RTL Component Info : --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4895] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:428] Finished RTL Component Statistics WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:435] --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:442] Hierarchical RTL Component report WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:4978] --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5061] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:449] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5144] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:456] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5227] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:463] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5310] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:477] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:505] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5476] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:519] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5559] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:533] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5642] Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 26691 ; free virtual = 52644 WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:540] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5725] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:547] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:554] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5808] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:568] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:568] Loading part: xc7z020clg400-1 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:610] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5891] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:617] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:5974] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:624] Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 26689 ; free virtual = 52642 WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:631] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6057] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:638] --------------------------------------------------------------------------------- WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6140] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:652] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6223] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:659] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6306] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:673] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6389] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:680] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6472] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:694] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6555] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:4] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1205.953 ; gain = 110.508 ; free physical = 26666 ; free virtual = 52619 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 26678 ; free virtual = 52631 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.496 ; free physical = 26663 ; free virtual = 52617 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 26644 ; free virtual = 52598 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.496 ; free physical = 26572 ; free virtual = 52527 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.523 ; free physical = 26569 ; free virtual = 52525 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 26554 ; free virtual = 52508 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 26549 ; free virtual = 52503 --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:671] INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 26495 ; free virtual = 52449 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.523 ; free physical = 26484 ; free virtual = 52439 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 26351 ; free virtual = 52305 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 26267 ; free virtual = 52220 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 26265 ; free virtual = 52218 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 26139 ; free virtual = 52092 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1227.941 ; gain = 132.332 ; free physical = 25977 ; free virtual = 51930 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1227.941 ; gain = 132.332 ; free physical = 25930 ; free virtual = 51884 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1235.969 ; gain = 140.359 ; free physical = 25929 ; free virtual = 51883 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 25269 ; free virtual = 51225 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 25260 ; free virtual = 51217 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 1267.961 ; gain = 172.352 ; free physical = 25260 ; free virtual = 51218 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- No constraint files found. Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 25257 ; free virtual = 51213 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 25249 ; free virtual = 51209 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 25244 ; free virtual = 51199 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 25237 ; free virtual = 51196 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 25238 ; free virtual = 51192 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 25234 ; free virtual = 51188 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 25231 ; free virtual = 51185 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25231 ; free virtual = 51188 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1305.926 ; gain = 210.480 ; free physical = 25231 ; free virtual = 51188 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 25230 ; free virtual = 51184 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25228 ; free virtual = 51182 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 25208 ; free virtual = 51167 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1305.926 ; gain = 210.480 ; free physical = 25206 ; free virtual = 51160 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 25200 ; free virtual = 51156 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 25190 ; free virtual = 51144 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1327.922 ; gain = 232.477 ; free physical = 25176 ; free virtual = 51130 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 25181 ; free virtual = 51135 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1327.922 ; gain = 232.477 ; free physical = 25180 ; free virtual = 51134 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.688 ; gain = 208.234 ; free physical = 25178 ; free virtual = 51132 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 25179 ; free virtual = 51133 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 25179 ; free virtual = 51133 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 25179 ; free virtual = 51133 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ --------------------------------------------------------------------------------- | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ Start IO Insertion +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 25178 ; free virtual = 51132 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 25178 ; free virtual = 51132 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 25178 ; free virtual = 51132 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 25178 ; free virtual = 51132 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 25178 ; free virtual = 51132 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 25178 ; free virtual = 51132 --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25179 ; free virtual = 51133 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.688 ; gain = 208.234 ; free physical = 25179 ; free virtual = 51133 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 25163 ; free virtual = 51117 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 25162 ; free virtual = 51116 Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 25159 ; free virtual = 51113 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 25158 ; free virtual = 51112 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 25158 ; free virtual = 51112 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 25157 ; free virtual = 51111 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 25157 ; free virtual = 51111 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 25157 ; free virtual = 51111 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 25158 ; free virtual = 51112 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 25158 ; free virtual = 51112 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 25158 ; free virtual = 51112 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 25160 ; free virtual = 51114 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 25137 ; free virtual = 51095 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25137 ; free virtual = 51091 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25139 ; free virtual = 51093 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25139 ; free virtual = 51093 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25139 ; free virtual = 51093 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25139 ; free virtual = 51093 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25139 ; free virtual = 51093 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25139 ; free virtual = 51092 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I0 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I1 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I2 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I3 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I4 to constant 0 WARNING: [Synth 8-3295] tying undriven pin dummy_lut:I5 to constant 0 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25139 ; free virtual = 51093 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25140 ; free virtual = 51094 --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25140 ; free virtual = 51094 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 25141 ; free virtual = 51095 --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25142 ; free virtual = 51096 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25142 ; free virtual = 51096 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25142 ; free virtual = 51096 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25142 ; free virtual = 51096 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |LUT6 | 1| |2 |IBUF | 96| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 97| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25142 ; free virtual = 51096 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 8 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 25142 ; free virtual = 51096 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 25144 ; free virtual = 51098 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 25113 ; free virtual = 51067 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 25113 ; free virtual = 51067 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 25113 ; free virtual = 51067 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 25113 ; free virtual = 51067 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 25113 ; free virtual = 51067 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 25113 ; free virtual = 51067 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 25113 ; free virtual = 51067 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 25113 ; free virtual = 51067 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.457 ; free physical = 25111 ; free virtual = 51065 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 25114 ; free virtual = 51068 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 25100 ; free virtual = 51054 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 25099 ; free virtual = 51053 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 25098 ; free virtual = 51052 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 25097 ; free virtual = 51051 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 25097 ; free virtual = 51051 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 25098 ; free virtual = 51052 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 25096 ; free virtual = 51049 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. INFO: [Project 1-570] Preparing netlist for logic optimization Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 25097 ; free virtual = 51051 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 25097 ; free virtual = 51051 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 25098 ; free virtual = 51052 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 25098 ; free virtual = 51052 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 25099 ; free virtual = 51053 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 25098 ; free virtual = 51052 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 25098 ; free virtual = 51052 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 25098 ; free virtual = 51052 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |SRL16E | 1| |3 |XADC | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 25098 ; free virtual = 51052 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. INFO: [Project 1-571] Translating synthesized netlist Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.938 ; gain = 242.492 ; free physical = 25086 ; free virtual = 51040 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1337.945 ; gain = 242.492 ; free physical = 25087 ; free virtual = 51041 WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 96 Unisim elements for replacement Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 25075 ; free virtual = 51029 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 25067 ; free virtual = 51021 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 25066 ; free virtual = 51020 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 25056 ; free virtual = 51010 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 25063 ; free virtual = 51017 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 25063 ; free virtual = 51017 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 25063 ; free virtual = 51017 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 25063 ; free virtual = 51017 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----------+------+ | |Cell |Count | +------+-----------+------+ |1 |IDELAYCTRL | 1| |2 |IDELAYE2 | 200| |3 |IBUF | 200| +------+-----------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 401| +------+---------+-------+------+ --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 25062 ; free virtual = 51016 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 402 warnings. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.211 ; free physical = 25061 ; free virtual = 51015 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.672 ; gain = 216.211 ; free physical = 25062 ; free virtual = 51016 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 25038 ; free virtual = 50992 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 25038 ; free virtual = 50992 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 25035 ; free virtual = 50988 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 25034 ; free virtual = 50988 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 25035 ; free virtual = 50988 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 25034 ; free virtual = 50988 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 25033 ; free virtual = 50987 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 25030 ; free virtual = 50984 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 25031 ; free virtual = 50985 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'dut_XADC_X0Y0' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 400 Unisim elements for replacement INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24909 ; free virtual = 50863 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24911 ; free virtual = 50865 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24906 ; free virtual = 50860 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24906 ; free virtual = 50860 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24905 ; free virtual = 50859 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24905 ; free virtual = 50858 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24904 ; free virtual = 50858 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24903 ; free virtual = 50857 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 24903 ; free virtual = 50857 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:21 . Memory (MB): peak = 1344.547 ; gain = 248.938 ; free physical = 24593 ; free virtual = 50547 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1344.547 ; gain = 248.938 ; free physical = 24596 ; free virtual = 50550 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1398.684 ; gain = 315.797 ; free physical = 24599 ; free virtual = 50553 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1396.688 ; gain = 313.797 ; free physical = 24602 ; free virtual = 50556 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 24425 ; free virtual = 50378 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 24423 ; free virtual = 50377 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 24422 ; free virtual = 50376 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ 14 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1396.691 ; gain = 313.797 ; free physical = 24426 ; free virtual = 50380 --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Looping LIOB33_X0Y1 0 IOB_X0Y1 {di[0]} key "IOB_X0Y1" not known in dictionary while executing "dict get $io_pin_sites $site" ("for" body line 17) invoked from within "for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { set line [lindex $pin_lines $idx] puts "$line" set site_str [linde..." (procedure "loc_pins" line 6) invoked from within "loc_pins" (procedure "run" line 6) invoked from within "run" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob/generate.tcl" line 77) INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:48:37 2019... 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1401.691 ; gain = 318.797 ; free physical = 24430 ; free virtual = 50384 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/top.v:2] INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_001/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob' Makefile:57: recipe for target 'iob/build/segbits_tilegrid.tdb' failed GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_002 Starting Placer Task 12 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1420.938 ; gain = 338.047 ; free physical = 24828 ; free virtual = 50787 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.723 ; gain = 0.000 ; free physical = 24827 ; free virtual = 50787 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1465.723 ; gain = 0.000 ; free physical = 24827 ; free virtual = 50787 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 24810 ; free virtual = 50773 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 24809 ; free virtual = 50772 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y0' at site IDELAY_X0Y0, Site IOB_X0Y0 is not bonded. Place terminal di[0] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:19] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y1' at site IDELAY_X0Y1, Site IOB_X0Y1 is not bonded. Place terminal di[14] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:187] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y2' at site IDELAY_X0Y2, Site IOB_X0Y2 is not bonded. Place terminal di[15] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:199] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y29' at site IDELAY_X0Y29, Site IOB_X0Y29 is not bonded. Place terminal di[30] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:379] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y3' at site IDELAY_X0Y3, Site IOB_X0Y3 is not bonded. Place terminal di[32] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:403] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y30' at site IDELAY_X0Y30, Site IOB_X0Y30 is not bonded. Place terminal di[31] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:391] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y31' at site IDELAY_X0Y31, Site IOB_X0Y31 is not bonded. Place terminal di[4] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:67] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y32' at site IDELAY_X0Y32, Site IOB_X0Y32 is not bonded. Place terminal di[5] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:79] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y33' at site IDELAY_X0Y33, Site IOB_X0Y33 is not bonded. Place terminal di[34] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:427] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y34' at site IDELAY_X0Y34, Site IOB_X0Y34 is not bonded. Place terminal di[35] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:439] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y35' at site IDELAY_X0Y35, Site IOB_X0Y35 is not bonded. Place terminal di[36] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:451] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y36' at site IDELAY_X0Y36, Site IOB_X0Y36 is not bonded. Place terminal di[37] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:463] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y38' at site IDELAY_X0Y38, Site IOB_X0Y38 is not bonded. Place terminal di[13] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:175] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y39' at site IDELAY_X0Y39, Site IOB_X0Y39 is not bonded. Place terminal di[38] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:475] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y4' at site IDELAY_X0Y4, Site IOB_X0Y4 is not bonded. Place terminal di[33] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:415] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y40' at site IDELAY_X0Y40, Site IOB_X0Y40 is not bonded. Place terminal di[39] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:487] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y41' at site IDELAY_X0Y41, Site IOB_X0Y41 is not bonded. Place terminal di[40] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:499] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y42' at site IDELAY_X0Y42, Site IOB_X0Y42 is not bonded. Place terminal di[41] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:511] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y43' at site IDELAY_X0Y43, Site IOB_X0Y43 is not bonded. Place terminal di[6] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:91] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y44' at site IDELAY_X0Y44, Site IOB_X0Y44 is not bonded. Place terminal di[7] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:103] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y45' at site IDELAY_X0Y45, Site IOB_X0Y45 is not bonded. Place terminal di[42] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:523] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y46' at site IDELAY_X0Y46, Site IOB_X0Y46 is not bonded. Place terminal di[43] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:535] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y47' at site IDELAY_X0Y47, Site IOB_X0Y47 is not bonded. Place terminal di[44] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:547] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y48' at site IDELAY_X0Y48, Site IOB_X0Y48 is not bonded. Place terminal di[45] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:559] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X0Y49' at site IDELAY_X0Y49, Site IOB_X0Y49 is not bonded. Place terminal di[1] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:31] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y0' at site IDELAY_X1Y0, Site IOB_X1Y0 is not bonded. Place terminal di[50] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:619] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y1' at site IDELAY_X1Y1, Site IOB_X1Y1 is not bonded. Place terminal di[92] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1123] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y10' at site IDELAY_X1Y10, Site IOB_X1Y10 is not bonded. Place terminal di[193] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:2335] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y11' at site IDELAY_X1Y11, Site IOB_X1Y11 is not bonded. Place terminal di[102] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1243] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y12' at site IDELAY_X1Y12, Site IOB_X1Y12 is not bonded. Place terminal di[103] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1255] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y13' at site IDELAY_X1Y13, Site IOB_X1Y13 is not bonded. Place terminal di[82] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1003] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y14' at site IDELAY_X1Y14, Site IOB_X1Y14 is not bonded. Place terminal di[83] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1015] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y15' at site IDELAY_X1Y15, Site IOB_X1Y15 is not bonded. Place terminal di[132] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1603] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y16' at site IDELAY_X1Y16, Site IOB_X1Y16 is not bonded. Place terminal di[133] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1615] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y17' at site IDELAY_X1Y17, Site IOB_X1Y17 is not bonded. Place terminal di[134] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1627] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y18' at site IDELAY_X1Y18, Site IOB_X1Y18 is not bonded. Place terminal di[135] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1639] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y19' at site IDELAY_X1Y19, Site IOB_X1Y19 is not bonded. Place terminal di[64] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:787] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y2' at site IDELAY_X1Y2, Site IOB_X1Y2 is not bonded. Place terminal di[93] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1135] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y20' at site IDELAY_X1Y20, Site IOB_X1Y20 is not bonded. Place terminal di[65] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:799] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y21' at site IDELAY_X1Y21, Site IOB_X1Y21 is not bonded. Place terminal di[136] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1651] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y22' at site IDELAY_X1Y22, Site IOB_X1Y22 is not bonded. Place terminal di[137] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1663] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y23' at site IDELAY_X1Y23, Site IOB_X1Y23 is not bonded. Place terminal di[138] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1675] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y24' at site IDELAY_X1Y24, Site IOB_X1Y24 is not bonded. Place terminal di[139] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1687] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y25' at site IDELAY_X1Y25, Site IOB_X1Y25 is not bonded. Place terminal di[140] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1699] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y26' at site IDELAY_X1Y26, Site IOB_X1Y26 is not bonded. Place terminal di[141] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1711] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y27' at site IDELAY_X1Y27, Site IOB_X1Y27 is not bonded. Place terminal di[142] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1723] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y28' at site IDELAY_X1Y28, Site IOB_X1Y28 is not bonded. Place terminal di[143] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1735] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y29' at site IDELAY_X1Y29, Site IOB_X1Y29 is not bonded. Place terminal di[144] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1747] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y3' at site IDELAY_X1Y3, Site IOB_X1Y3 is not bonded. Place terminal di[146] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1771] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y30' at site IDELAY_X1Y30, Site IOB_X1Y30 is not bonded. Place terminal di[145] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1759] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y31' at site IDELAY_X1Y31, Site IOB_X1Y31 is not bonded. Place terminal di[66] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:811] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y32' at site IDELAY_X1Y32, Site IOB_X1Y32 is not bonded. Place terminal di[67] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:823] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y33' at site IDELAY_X1Y33, Site IOB_X1Y33 is not bonded. Place terminal di[148] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1795] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y34' at site IDELAY_X1Y34, Site IOB_X1Y34 is not bonded. Place terminal di[149] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1807] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y35' at site IDELAY_X1Y35, Site IOB_X1Y35 is not bonded. Place terminal di[150] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1819] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y36' at site IDELAY_X1Y36, Site IOB_X1Y36 is not bonded. Place terminal di[151] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1831] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y37' at site IDELAY_X1Y37, Site IOB_X1Y37 is not bonded. Place terminal di[86] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1051] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y38' at site IDELAY_X1Y38, Site IOB_X1Y38 is not bonded. Place terminal di[87] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1063] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y39' at site IDELAY_X1Y39, Site IOB_X1Y39 is not bonded. Place terminal di[152] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1843] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y4' at site IDELAY_X1Y4, Site IOB_X1Y4 is not bonded. Place terminal di[147] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1783] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y40' at site IDELAY_X1Y40, Site IOB_X1Y40 is not bonded. Place terminal di[153] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1855] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y41' at site IDELAY_X1Y41, Site IOB_X1Y41 is not bonded. Place terminal di[154] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1867] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y42' at site IDELAY_X1Y42, Site IOB_X1Y42 is not bonded. Place terminal di[155] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1879] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y43' at site IDELAY_X1Y43, Site IOB_X1Y43 is not bonded. Place terminal di[68] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:835] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y44' at site IDELAY_X1Y44, Site IOB_X1Y44 is not bonded. Place terminal di[69] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:847] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y45' at site IDELAY_X1Y45, Site IOB_X1Y45 is not bonded. Place terminal di[156] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1891] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y46' at site IDELAY_X1Y46, Site IOB_X1Y46 is not bonded. Place terminal di[157] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1903] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y47' at site IDELAY_X1Y47, Site IOB_X1Y47 is not bonded. Place terminal di[158] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1915] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y48' at site IDELAY_X1Y48, Site IOB_X1Y48 is not bonded. Place terminal di[159] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1927] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y49' at site IDELAY_X1Y49, Site IOB_X1Y49 is not bonded. Place terminal di[53] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:655] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y5' at site IDELAY_X1Y5, Site IOB_X1Y5 is not bonded. Place terminal di[160] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1939] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y6' at site IDELAY_X1Y6, Site IOB_X1Y6 is not bonded. Place terminal di[161] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:1951] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y7' at site IDELAY_X1Y7, Site IOB_X1Y7 is not bonded. Place terminal di[74] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:907] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y8' at site IDELAY_X1Y8, Site IOB_X1Y8 is not bonded. Place terminal di[75] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:919] CRITICAL WARNING: [Constraints 18-5] Cannot loc instance 'idelay_IDELAY_X1Y9' at site IDELAY_X1Y9, Site IOB_X1Y9 is not bonded. Place terminal di[192] and connected instances in a site with a PAD [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/build/specimen_001/top.v:2323] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 24698 ; free virtual = 50672 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 24697 ; free virtual = 50671 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- 18 Infos, 200 Warnings, 75 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1399.688 ; gain = 316.797 ; free physical = 24746 ; free virtual = 50721 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1404.926 ; gain = 322.039 ; free physical = 24753 ; free virtual = 50728 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Looping INT_L_X0Y0 0 IDELAY_X0Y0 IOB_X0Y0 {di[0]} key "IOB_X0Y0" not known in dictionary while executing "dict get $io_pin_sites $site" ("for" body line 17) invoked from within "for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { set line [lindex $pin_lines $idx] puts "$line" set site_str [linde..." (procedure "loc_pins" line 6) invoked from within "loc_pins" (procedure "run" line 6) invoked from within "run" (file "/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int/generate.tcl" line 75) INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:48:38 2019... --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 24758 ; free virtual = 50732 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 24759 ; free virtual = 50734 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 24760 ; free virtual = 50734 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 24760 ; free virtual = 50735 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 24761 ; free virtual = 50736 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.570 ; gain = 269.961 ; free physical = 24761 ; free virtual = 50735 Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 24775 ; free virtual = 50750 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 24820 ; free virtual = 50776 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 13 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 25259 ; free virtual = 51214 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_001/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/iob_int' Makefile:60: recipe for target 'iob_int/build/segbits_tilegrid.tdb' failed GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting Placer Task 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 25346 ; free virtual = 51301 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1484.969 ; gain = 0.000 ; free physical = 25344 ; free virtual = 51299 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c83132f2 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1484.969 ; gain = 0.000 ; free physical = 25344 ; free virtual = 51299 INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.957 ; gain = 0.000 ; free physical = 25255 ; free virtual = 51230 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1470.957 ; gain = 0.000 ; free physical = 25246 ; free virtual = 51221 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 25216 ; free virtual = 51191 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1583c4629 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 25216 ; free virtual = 51191 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 25234 ; free virtual = 51189 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 25234 ; free virtual = 51189 --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 25230 ; free virtual = 51185 INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1471.957 ; gain = 0.000 ; free physical = 25207 ; free virtual = 51163 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 25169 ; free virtual = 51125 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 25059 ; free virtual = 51014 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 25056 ; free virtual = 51011 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1335.066 ; gain = 239.152 ; free physical = 24819 ; free virtual = 50774 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:33 . Memory (MB): peak = 1339.098 ; gain = 243.184 ; free physical = 24646 ; free virtual = 50601 --------------------------------------------------------------------------------- 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 1467.242 ; gain = 384.359 ; free physical = 24649 ; free virtual = 50605 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:34 ; elapsed = 00:00:33 . Memory (MB): peak = 1339.098 ; gain = 243.184 ; free physical = 24581 ; free virtual = 50537 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1547.945 ; gain = 0.000 ; free physical = 24405 ; free virtual = 50360 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:34 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 24441 ; free virtual = 50396 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.40 . Memory (MB): peak = 1547.945 ; gain = 0.000 ; free physical = 24430 ; free virtual = 50385 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 24380 ; free virtual = 50336 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 24348 ; free virtual = 50303 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 24362 ; free virtual = 50317 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 24358 ; free virtual = 50313 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 24353 ; free virtual = 50309 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 24351 ; free virtual = 50307 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 24351 ; free virtual = 50306 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 1347.074 ; gain = 251.160 ; free physical = 24350 ; free virtual = 50305 Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:00:36 . Memory (MB): peak = 1347.082 ; gain = 251.160 ; free physical = 24351 ; free virtual = 50307 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.207 ; gain = 0.000 ; free physical = 23931 ; free virtual = 49887 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 23870 ; free virtual = 49826 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 23897 ; free virtual = 49852 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 23897 ; free virtual = 49852 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 23897 ; free virtual = 49852 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 23897 ; free virtual = 49852 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 23898 ; free virtual = 49853 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1904.250 ; gain = 507.562 ; free physical = 23898 ; free virtual = 49853 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1843.203 ; gain = 0.000 ; free physical = 23287 ; free virtual = 49243 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.211 ; gain = 0.000 ; free physical = 23143 ; free virtual = 49098 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 23071 ; free virtual = 49026 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 23071 ; free virtual = 49026 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 23071 ; free virtual = 49026 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 23070 ; free virtual = 49026 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 23070 ; free virtual = 49026 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.254 ; gain = 435.531 ; free physical = 23071 ; free virtual = 49026 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1901.254 ; gain = 499.562 ; free physical = 23071 ; free virtual = 49026 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 22894 ; free virtual = 48850 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 22861 ; free virtual = 48816 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 22855 ; free virtual = 48811 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 22850 ; free virtual = 48806 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 22845 ; free virtual = 48800 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 22836 ; free virtual = 48792 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 532.562 ; free physical = 22835 ; free virtual = 48790 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Routing Task INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1851.457 ; gain = 0.000 ; free physical = 22403 ; free virtual = 48358 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1898.445 ; gain = 0.000 ; free physical = 22241 ; free virtual = 48196 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 22044 ; free virtual = 48000 WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 1.3 Build Placer Netlist Model report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 22039 ; free virtual = 47994 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 22038 ; free virtual = 47993 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 22033 ; free virtual = 47988 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 22030 ; free virtual = 47985 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.488 ; gain = 515.531 ; free physical = 22027 ; free virtual = 47982 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.488 ; gain = 581.562 ; free physical = 22025 ; free virtual = 47981 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 22021 ; free virtual = 47977 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd81a835 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1939.500 ; gain = 454.531 ; free physical = 22015 ; free virtual = 47970 Phase 1.3 Build Placer Netlist Model Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.3 Build Placer Netlist Model | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1939.500 ; gain = 454.531 ; free physical = 22004 ; free virtual = 47959 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1939.500 ; gain = 454.531 ; free physical = 21999 ; free virtual = 47954 Phase 1 Placer Initialization | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1939.500 ; gain = 454.531 ; free physical = 21998 ; free virtual = 47953 Phase 2 Global Placement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: Launching helper process for spawning children vivado processes Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 10b00cead Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 21910 ; free virtual = 47865 Phase 1.3 Build Placer Netlist Model INFO: Helper process launched with PID 6264 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.3 Build Placer Netlist Model | Checksum: 1a2533493 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 21905 ; free virtual = 47860 Phase 1.4 Constrain Clocks/Macros Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 21904 ; free virtual = 47859 Phase 1.4 Constrain Clocks/Macros | Checksum: 1a2533493 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 21904 ; free virtual = 47859 Phase 1 Placer Initialization | Checksum: 1a2533493 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 21899 ; free virtual = 47855 Phase 2 Global Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 6634 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 21798 ; free virtual = 47754 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 21809 ; free virtual = 47765 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 21804 ; free virtual = 47759 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 21798 ; free virtual = 47753 Phase 2 Final Placement Cleanup Starting Routing Task Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 21788 ; free virtual = 47743 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.488 ; gain = 519.531 ; free physical = 21774 ; free virtual = 47730 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 21766 ; free virtual = 47721 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.227 ; gain = 0.000 ; free physical = 21459 ; free virtual = 47414 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 21368 ; free virtual = 47324 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 21336 ; free virtual = 47292 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 21324 ; free virtual = 47280 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 21305 ; free virtual = 47261 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 21299 ; free virtual = 47255 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 21297 ; free virtual = 47253 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 577.562 ; free physical = 21297 ; free virtual = 47253 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Global Placement | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21251 ; free virtual = 47206 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21248 ; free virtual = 47204 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 16b25666e Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21247 ; free virtual = 47203 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1dee41518 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21241 ; free virtual = 47197 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 175ba2c6b Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21241 ; free virtual = 47197 Phase 3.5 Small Shape Detail Placement Phase 2 Global Placement | Checksum: 19a3c3d56 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21224 ; free virtual = 47180 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 19a3c3d56 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21222 ; free virtual = 47177 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.5 Small Shape Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21223 ; free virtual = 47178 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21223 ; free virtual = 47179 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21223 ; free virtual = 47179 Phase 3 Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21223 ; free virtual = 47179 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21222 ; free virtual = 47178 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21222 ; free virtual = 47177 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21221 ; free virtual = 47177 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21221 ; free virtual = 47177 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21221 ; free virtual = 47177 Ending Placer Task | Checksum: 584e5438 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.547 ; gain = 550.578 ; free physical = 21234 ; free virtual = 47190 22 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.547 ; gain = 614.609 ; free physical = 21234 ; free virtual = 47189 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d4686e25 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21234 ; free virtual = 47189 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1ae434bf0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21231 ; free virtual = 47187 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 177f7ac55 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21231 ; free virtual = 47187 Phase 3.5 Small Shape Detail Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 3.5 Small Shape Detail Placement | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21193 ; free virtual = 47149 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21193 ; free virtual = 47148 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21192 ; free virtual = 47148 Phase 3 Detail Placement | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21184 ; free virtual = 47140 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21171 ; free virtual = 47127 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21171 ; free virtual = 47126 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21170 ; free virtual = 47126 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21168 ; free virtual = 47124 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 209030315 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21168 ; free virtual = 47124 Ending Placer Task | Checksum: 1c0d5e9dc Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 21180 ; free virtual = 47136 23 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 21180 ; free virtual = 47135 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 248660b8 ConstDB: 0 ShapeSum: 33c7f380 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: dc3640d2 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 20856 ; free virtual = 46812 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 20513 ; free virtual = 46469 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 20445 ; free virtual = 46401 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 20444 ; free virtual = 46400 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 20432 ; free virtual = 46388 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 20410 ; free virtual = 46366 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.434 ; gain = 0.000 ; free physical = 20310 ; free virtual = 46266 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:456] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20169 ; free virtual = 46125 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20150 ; free virtual = 46106 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20149 ; free virtual = 46106 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20131 ; free virtual = 46087 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.148 ; gain = 455.203 ; free physical = 20079 ; free virtual = 46035 Phase 1.3 Build Placer Netlist Model INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:01:02 . Memory (MB): peak = 1476.832 ; gain = 393.945 ; free physical = 19862 ; free virtual = 45819 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.148 ; gain = 455.203 ; free physical = 19841 ; free virtual = 45797 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.148 ; gain = 455.203 ; free physical = 19808 ; free virtual = 45764 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.148 ; gain = 455.203 ; free physical = 19774 ; free virtual = 45731 Phase 2 Global Placement Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 19763 ; free virtual = 45719 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 19776 ; free virtual = 45732 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19774 ; free virtual = 45730 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1557.863 ; gain = 0.000 ; free physical = 19759 ; free virtual = 45715 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1557.863 ; gain = 0.000 ; free physical = 19756 ; free virtual = 45713 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19730 ; free virtual = 45686 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19729 ; free virtual = 45685 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19729 ; free virtual = 45685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19729 ; free virtual = 45685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19729 ; free virtual = 45685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19729 ; free virtual = 45685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19728 ; free virtual = 45684 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19728 ; free virtual = 45684 Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 19728 ; free virtual = 45685 INFO: [Project 1-571] Translating synthesized netlist Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19714 ; free virtual = 45670 INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19705 ; free virtual = 45662 Phase 3.2 Commit Most Macros & LUTRAMs Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19690 ; free virtual = 45646 Phase 3.3 Area Swap Optimization No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 19677 ; free virtual = 45634 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 19675 ; free virtual = 45631 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19675 ; free virtual = 45631 Phase 3.4 Pipeline Register Optimization --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19674 ; free virtual = 45630 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19671 ; free virtual = 45628 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19655 ; free virtual = 45611 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19654 ; free virtual = 45610 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19652 ; free virtual = 45608 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19651 ; free virtual = 45607 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19649 ; free virtual = 45606 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19649 ; free virtual = 45605 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19649 ; free virtual = 45605 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19647 ; free virtual = 45604 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 19648 ; free virtual = 45604 INFO: [Project 1-571] Translating synthesized netlist Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19586 ; free virtual = 45542 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19572 ; free virtual = 45529 Phase 3.7 Pipeline Register Optimization INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19564 ; free virtual = 45520 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3 Detail Placement | Checksum: 181723f81 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19553 ; free virtual = 45509 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 1396.684 ; gain = 313.797 ; free physical = 19583 ; free virtual = 45539 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19581 ; free virtual = 45537 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.2 Post Placement Cleanup INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19573 ; free virtual = 45529 Phase 4.3 Placer Reporting Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 19571 ; free virtual = 45527 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 19571 ; free virtual = 45527 Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19565 ; free virtual = 45522 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19557 ; free virtual = 45513 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19549 ; free virtual = 45505 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.195 ; gain = 551.250 ; free physical = 19582 ; free virtual = 45538 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.195 ; gain = 631.953 ; free physical = 19582 ; free virtual = 45538 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 19459 ; free virtual = 45415 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 19423 ; free virtual = 45379 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 19421 ; free virtual = 45378 Phase 1 Build RT Design | Checksum: a00a49b6 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2055.934 ; gain = 119.668 ; free physical = 19199 ; free virtual = 45155 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: a00a49b6 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2060.922 ; gain = 124.656 ; free physical = 19125 ; free virtual = 45081 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: a00a49b6 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2060.922 ; gain = 124.656 ; free physical = 19125 ; free virtual = 45081 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1439f5939 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 19113 ; free virtual = 45069 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 19128 ; free virtual = 45085 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 19127 ; free virtual = 45084 Phase 4 Rip-up And Reroute | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 19127 ; free virtual = 45084 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 19127 ; free virtual = 45084 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 19127 ; free virtual = 45083 Phase 6 Post Hold Fix | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 19127 ; free virtual = 45083 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 19110 ; free virtual = 45066 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 19109 ; free virtual = 45065 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1439f5939 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 19109 ; free virtual = 45065 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 19142 ; free virtual = 45098 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2108.766 ; gain = 204.516 ; free physical = 19142 ; free virtual = 45098 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2108.766 ; gain = 0.000 ; free physical = 19131 ; free virtual = 45088 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: d50581c6 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2056.930 ; gain = 93.668 ; free physical = 18920 ; free virtual = 44876 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: d50581c6 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2061.918 ; gain = 98.656 ; free physical = 18891 ; free virtual = 44847 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: d50581c6 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2061.918 ; gain = 98.656 ; free physical = 18891 ; free virtual = 44847 INFO: [Timing 38-35] Done setting XDC timing constraints. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 124d36534 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 18884 ; free virtual = 44840 Phase 3 Initial Routing INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 124d36534 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 18879 ; free virtual = 44835 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 124d36534 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 18878 ; free virtual = 44835 Phase 4 Rip-up And Reroute | Checksum: 124d36534 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 18878 ; free virtual = 44835 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 124d36534 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 18878 ; free virtual = 44835 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 124d36534 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 18878 ; free virtual = 44835 Phase 6 Post Hold Fix | Checksum: 124d36534 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 18878 ; free virtual = 44835 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 1 Build RT Design | Checksum: e50efac9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2054.938 ; gain = 121.668 ; free physical = 18872 ; free virtual = 44829 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 18872 ; free virtual = 44829 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 124d36534 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2071.973 ; gain = 108.711 ; free physical = 18871 ; free virtual = 44827 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 124d36534 Phase 2 Router Initialization Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2071.973 ; gain = 108.711 ; free physical = 18872 ; free virtual = 44828 INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1963.352 ; gain = 0.000 ; free physical = 18877 ; free virtual = 44833 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2071.973 ; gain = 108.711 ; free physical = 18899 ; free virtual = 44855 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2110.762 ; gain = 179.516 ; free physical = 18896 ; free virtual = 44852 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: e50efac9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2058.926 ; gain = 125.656 ; free physical = 18886 ; free virtual = 44842 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: e50efac9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2058.926 ; gain = 125.656 ; free physical = 18882 ; free virtual = 44839 Writing placer database... Writing XDEF routing. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 18859 ; free virtual = 44817 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18e90f676 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 18840 ; free virtual = 44797 Phase 3 Initial Routing WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 18775 ; free virtual = 44732 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 18790 ; free virtual = 44746 Phase 4 Rip-up And Reroute | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 18790 ; free virtual = 44747 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 18791 ; free virtual = 44747 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 18791 ; free virtual = 44748 Phase 6 Post Hold Fix | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 18791 ; free virtual = 44748 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2065.980 ; gain = 132.711 ; free physical = 18783 ; free virtual = 44739 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.980 ; gain = 135.711 ; free physical = 18782 ; free virtual = 44739 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 18e90f676 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.980 ; gain = 135.711 ; free physical = 18783 ; free virtual = 44740 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.980 ; gain = 135.711 ; free physical = 18825 ; free virtual = 44782 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2107.770 ; gain = 206.516 ; free physical = 18832 ; free virtual = 44789 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2107.770 ; gain = 0.000 ; free physical = 18816 ; free virtual = 44774 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2062.172 ; gain = 43.668 ; free physical = 18784 ; free virtual = 44742 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.160 ; gain = 48.656 ; free physical = 18736 ; free virtual = 44693 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2067.160 ; gain = 48.656 ; free physical = 18734 ; free virtual = 44691 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2051.395 ; gain = 493.531 ; free physical = 18708 ; free virtual = 44665 Phase 1.3 Build Placer Netlist Model Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2078.215 ; gain = 59.711 ; free physical = 18710 ; free virtual = 44667 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 18680 ; free virtual = 44636 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 18674 ; free virtual = 44631 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 18672 ; free virtual = 44629 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 18667 ; free virtual = 44624 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 18663 ; free virtual = 44620 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 18660 ; free virtual = 44617 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2080.215 ; gain = 61.711 ; free physical = 18618 ; free virtual = 44575 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2083.215 ; gain = 64.711 ; free physical = 18622 ; free virtual = 44579 Phase 9 Depositing Routes WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2083.215 ; gain = 64.711 ; free physical = 18625 ; free virtual = 44582 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2083.215 ; gain = 64.711 ; free physical = 18660 ; free virtual = 44617 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2122.004 ; gain = 135.516 ; free physical = 18654 ; free virtual = 44611 Writing placer database... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2122.004 ; gain = 0.000 ; free physical = 18632 ; free virtual = 44591 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.203 ; gain = 0.000 ; free physical = 18355 ; free virtual = 44313 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 18330 ; free virtual = 44287 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 18321 ; free virtual = 44279 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 18321 ; free virtual = 44279 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 18321 ; free virtual = 44279 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 18321 ; free virtual = 44279 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 18322 ; free virtual = 44279 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 507.562 ; free physical = 18322 ; free virtual = 44279 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.172 ; gain = 43.668 ; free physical = 18307 ; free virtual = 44264 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 18276 ; free virtual = 44233 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 18279 ; free virtual = 44237 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 18167 ; free virtual = 44125 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 18135 ; free virtual = 44092 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 18111 ; free virtual = 44068 Loading data files... Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 18108 ; free virtual = 44065 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 18105 ; free virtual = 44063 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 18104 ; free virtual = 44062 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 18103 ; free virtual = 44060 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2086.465 ; gain = 62.961 ; free physical = 18079 ; free virtual = 44037 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 18076 ; free virtual = 44033 Phase 9 Depositing Routes WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 18081 ; free virtual = 44038 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2089.465 ; gain = 65.961 ; free physical = 18125 ; free virtual = 44083 Routing Is Done. Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2128.254 ; gain = 136.766 ; free physical = 18127 ; free virtual = 44085 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2051.395 ; gain = 493.531 ; free physical = 18127 ; free virtual = 44084 Phase 1.4 Constrain Clocks/Macros Writing placer database... Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2051.395 ; gain = 493.531 ; free physical = 18112 ; free virtual = 44070 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2051.395 ; gain = 493.531 ; free physical = 18064 ; free virtual = 44024 Phase 2 Final Placement Cleanup Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2128.254 ; gain = 0.000 ; free physical = 18054 ; free virtual = 44014 Phase 1 Build RT Design | Checksum: edf89240 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2068.953 ; gain = 42.668 ; free physical = 18051 ; free virtual = 44012 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: edf89240 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 18012 ; free virtual = 43970 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: edf89240 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 18011 ; free virtual = 43969 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2051.395 ; gain = 493.531 ; free physical = 18005 ; free virtual = 43963 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2051.395 ; gain = 493.531 ; free physical = 18012 ; free virtual = 43970 Loading data files... 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2051.395 ; gain = 574.562 ; free physical = 18000 ; free virtual = 43958 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1446d92b6 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2087.371 ; gain = 61.086 ; free physical = 17922 ; free virtual = 43880 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 1501539a8 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2070.188 ; gain = 34.641 ; free physical = 17886 ; free virtual = 43844 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.371 ; gain = 62.086 ; free physical = 17858 ; free virtual = 43816 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1501539a8 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2075.176 ; gain = 39.629 ; free physical = 17835 ; free virtual = 43793 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1501539a8 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2075.176 ; gain = 39.629 ; free physical = 17835 ; free virtual = 43793 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.371 ; gain = 62.086 ; free physical = 17822 ; free virtual = 43780 Phase 4 Rip-up And Reroute | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.371 ; gain = 62.086 ; free physical = 17819 ; free virtual = 43777 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.371 ; gain = 62.086 ; free physical = 17813 ; free virtual = 43771 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.371 ; gain = 62.086 ; free physical = 17807 ; free virtual = 43765 Phase 6 Post Hold Fix | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.371 ; gain = 62.086 ; free physical = 17802 ; free virtual = 43760 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2088.371 ; gain = 62.086 ; free physical = 17688 ; free virtual = 43646 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2091.371 ; gain = 65.086 ; free physical = 17678 ; free virtual = 43637 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1446d92b6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2091.371 ; gain = 65.086 ; free physical = 17676 ; free virtual = 43634 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2091.371 ; gain = 65.086 ; free physical = 17715 ; free virtual = 43673 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:46 . Memory (MB): peak = 2130.160 ; gain = 135.891 ; free physical = 17711 ; free virtual = 43669 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Writing placer database... Phase 1 Build RT Design | Checksum: 14af9d38a Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 17665 ; free virtual = 43624 Writing XDEF routing. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: d17cc5cd Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 17658 ; free virtual = 43618 Phase 3 Initial Routing Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Write XDEF Complete: Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2130.160 ; gain = 0.000 ; free physical = 17625 ; free virtual = 43586 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 14af9d38a Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 17621 ; free virtual = 43582 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 14af9d38a Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 17617 ; free virtual = 43577 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 17570 ; free virtual = 43531 Loading data files... Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 17562 ; free virtual = 43524 Phase 4 Rip-up And Reroute | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 17561 ; free virtual = 43522 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 17558 ; free virtual = 43520 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 17556 ; free virtual = 43518 Phase 6 Post Hold Fix | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 17555 ; free virtual = 43516 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 17571 ; free virtual = 43533 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 17569 ; free virtual = 43531 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 17569 ; free virtual = 43531 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2095.230 ; gain = 59.684 ; free physical = 17601 ; free virtual = 43560 Routing Is Done. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' 29 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2134.020 ; gain = 98.473 ; free physical = 17598 ; free virtual = 43556 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2134.020 ; gain = 0.000 ; free physical = 17524 ; free virtual = 43484 Number of Nodes with overlaps = 0 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Router Initialization | Checksum: b9dafcfc Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 17492 ; free virtual = 43451 Phase 3 Initial Routing INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 17242 ; free virtual = 43201 Phase 1 Build RT Design Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 17220 ; free virtual = 43179 Phase 4 Rip-up And Reroute | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 17211 ; free virtual = 43170 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 17205 ; free virtual = 43164 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 17205 ; free virtual = 43164 Phase 6 Post Hold Fix | Checksum: 12510dc3b Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 17204 ; free virtual = 43163 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 17202 ; free virtual = 43161 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 17187 ; free virtual = 43146 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12510dc3b Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 17233 ; free virtual = 43192 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.227 ; gain = 8.684 ; free physical = 17276 ; free virtual = 43235 Routing Is Done. 30 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:45 . Memory (MB): peak = 2140.016 ; gain = 47.473 ; free physical = 17278 ; free virtual = 43237 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2140.016 ; gain = 0.000 ; free physical = 17273 ; free virtual = 43234 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.449 ; gain = 0.000 ; free physical = 17256 ; free virtual = 43218 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 17045 ; free virtual = 43004 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 17072 ; free virtual = 43031 Phase 1.4 Constrain Clocks/Macros Running DRC as a precondition to command write_bitstream Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 17066 ; free virtual = 43025 Command: report_drc (run_mandatory_drcs) for: bitstream_checks Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 17055 ; free virtual = 43015 Phase 2 Final Placement Cleanup INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 17044 ; free virtual = 43003 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1990.492 ; gain = 518.531 ; free physical = 17055 ; free virtual = 43014 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.492 ; gain = 583.562 ; free physical = 17056 ; free virtual = 43015 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Creating bitstream... Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... Loading data files... Loading route data... Processing options... Creating bitmap... Loading site data... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... Creating bitstream... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... Loading site data... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:50:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 2450.871 ; gain = 342.105 ; free physical = 16142 ; free virtual = 42114 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:50:02 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading site data... touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_003 Loading route data... Processing options... Creating bitmap... Loading site data... Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:50:05 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 2452.875 ; gain = 345.105 ; free physical = 16967 ; free virtual = 42939 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:50:05 2019... Loading route data... Processing options... Creating bitmap... Loading route data... Processing options... Creating bitmap... Creating bitstream... Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:50:06 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2454.867 ; gain = 344.105 ; free physical = 17867 ; free virtual = 43839 touch build/specimen_001/OK INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:50:06 2019... GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_002 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading site data... touch build/specimen_001/OK Creating bitstream... GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2128.953 ; gain = 29.758 ; free physical = 19724 ; free virtual = 45707 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2134.941 ; gain = 35.746 ; free physical = 19693 ; free virtual = 45677 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2134.941 ; gain = 35.746 ; free physical = 19693 ; free virtual = 45677 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:50:13 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 244 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2471.359 ; gain = 343.105 ; free physical = 19701 ; free virtual = 45684 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:50:13 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:50:13 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2461.109 ; gain = 339.105 ; free physical = 19720 ; free virtual = 45704 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:50:14 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2153.996 ; gain = 54.801 ; free physical = 19830 ; free virtual = 45813 Phase 3 Initial Routing Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2153.996 ; gain = 54.801 ; free physical = 21680 ; free virtual = 47663 DONE Bitstream size: 4243411 bytes Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2153.996 ; gain = 54.801 ; free physical = 21682 ; free virtual = 47666 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2153.996 ; gain = 54.801 ; free physical = 21681 ; free virtual = 47665 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2153.996 ; gain = 54.801 ; free physical = 21681 ; free virtual = 47665 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2153.996 ; gain = 54.801 ; free physical = 21680 ; free virtual = 47664 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2153.996 ; gain = 54.801 ; free physical = 21679 ; free virtual = 47663 Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2153.996 ; gain = 54.801 ; free physical = 21674 ; free virtual = 47657 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2153.996 ; gain = 54.801 ; free physical = 21672 ; free virtual = 47656 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2153.996 ; gain = 54.801 ; free physical = 21672 ; free virtual = 47655 Creating bitstream... INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2153.996 ; gain = 54.801 ; free physical = 21707 ; free virtual = 47691 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 2192.785 ; gain = 93.590 ; free physical = 21706 ; free virtual = 47690 touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_002 Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:50:15 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 39 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 2467.125 ; gain = 333.105 ; free physical = 21607 ; free virtual = 47595 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:50:15 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dframe 1C --dword 53 --dbit 24" bash ../fuzzaddr/generate.sh build/specimen_002 Writing bitstream ./design.bit... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2192.785 ; gain = 0.000 ; free physical = 23191 ; free virtual = 49207 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:50:20 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 2469.266 ; gain = 339.105 ; free physical = 23015 ; free virtual = 49008 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:50:20 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:50:20 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2475.121 ; gain = 335.105 ; free physical = 23050 ; free virtual = 49044 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:50:20 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_002 touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: aa30cc8b Time (s): cpu = 00:00:38 ; elapsed = 00:00:41 . Memory (MB): peak = 2056.930 ; gain = 120.668 ; free physical = 24517 ; free virtual = 50514 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: aa30cc8b Time (s): cpu = 00:00:38 ; elapsed = 00:00:41 . Memory (MB): peak = 2060.918 ; gain = 124.656 ; free physical = 24510 ; free virtual = 50507 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: aa30cc8b Time (s): cpu = 00:00:38 ; elapsed = 00:00:41 . Memory (MB): peak = 2060.918 ; gain = 124.656 ; free physical = 24510 ; free virtual = 50507 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9730 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1c45c954e Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 24505 ; free virtual = 50502 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1c45c954e Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 24414 ; free virtual = 50411 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1c45c954e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 24403 ; free virtual = 50399 Phase 4 Rip-up And Reroute | Checksum: 1c45c954e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 24402 ; free virtual = 50399 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1c45c954e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 24402 ; free virtual = 50398 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1c45c954e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 24402 ; free virtual = 50398 Phase 6 Post Hold Fix | Checksum: 1c45c954e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 24401 ; free virtual = 50398 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1c45c954e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 24339 ; free virtual = 50335 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1c45c954e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2070.973 ; gain = 134.711 ; free physical = 24347 ; free virtual = 50343 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1c45c954e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2070.973 ; gain = 134.711 ; free physical = 24360 ; free virtual = 50357 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2070.973 ; gain = 134.711 ; free physical = 24394 ; free virtual = 50391 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2109.762 ; gain = 205.516 ; free physical = 24394 ; free virtual = 50391 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2109.762 ; gain = 0.000 ; free physical = 24461 ; free virtual = 50459 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9774 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9784 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Phase 1 Build RT Design | Checksum: e91ff6d7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2135.078 ; gain = 51.668 ; free physical = 24003 ; free virtual = 50000 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: e91ff6d7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2144.066 ; gain = 60.656 ; free physical = 23920 ; free virtual = 49917 Phase 2.2 Pre Route Cleanup ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 2.2 Pre Route Cleanup | Checksum: e91ff6d7 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2144.066 ; gain = 60.656 ; free physical = 23913 ; free virtual = 49910 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading site data... Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18fae605e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 23636 ; free virtual = 49632 Phase 3 Initial Routing Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3 Initial Routing | Checksum: 18fae605e Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 23503 ; free virtual = 49500 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18fae605e Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 23490 ; free virtual = 49487 Phase 4 Rip-up And Reroute | Checksum: 18fae605e Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 23488 ; free virtual = 49485 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18fae605e Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 23526 ; free virtual = 49523 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 6.1 Hold Fix Iter | Checksum: 18fae605e Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 23562 ; free virtual = 49559 Phase 6 Post Hold Fix | Checksum: 18fae605e Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 23560 ; free virtual = 49557 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18fae605e Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 23518 ; free virtual = 49515 Phase 8 Verifying routed nets Verification completed successfully INFO: Launching helper process for spawning children vivado processes Phase 8 Verifying routed nets | Checksum: 18fae605e Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 23520 ; free virtual = 49517 Phase 9 Depositing Routes INFO: Helper process launched with PID 9866 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9882 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 23528 ; free virtual = 49525 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 18fae605e Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 23506 ; free virtual = 49503 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 23542 ; free virtual = 49539 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:47 . Memory (MB): peak = 2218.285 ; gain = 166.891 ; free physical = 23541 ; free virtual = 49538 Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.176 ; gain = 45.668 ; free physical = 23531 ; free virtual = 49528 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2074.164 ; gain = 51.656 ; free physical = 23465 ; free virtual = 49462 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2074.164 ; gain = 51.656 ; free physical = 23461 ; free virtual = 49458 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing placer database... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 23352 ; free virtual = 49355 Phase 3 Initial Routing Creating bitstream... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9943 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 23349 ; free virtual = 49354 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 23348 ; free virtual = 49353 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 23348 ; free virtual = 49353 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 23348 ; free virtual = 49353 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 23347 ; free virtual = 49353 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 23347 ; free virtual = 49353 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2086.469 ; gain = 63.961 ; free physical = 23339 ; free virtual = 49346 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 23336 ; free virtual = 49343 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.469 ; gain = 66.961 ; free physical = 23321 ; free virtual = 49329 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.469 ; gain = 66.961 ; free physical = 23355 ; free virtual = 49363 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2128.258 ; gain = 137.766 ; free physical = 23354 ; free virtual = 49361 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:232] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:505] Writing placer database... WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/top.v:2] Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 23355 ; free virtual = 49370 --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2128.258 ; gain = 0.000 ; free physical = 23355 ; free virtual = 49370 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 23356 ; free virtual = 49370 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 23357 ; free virtual = 49371 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 23356 ; free virtual = 49369 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 23347 ; free virtual = 49361 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 23349 ; free virtual = 49363 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2218.285 ; gain = 0.000 ; free physical = 23127 ; free virtual = 49156 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/top.v:2] INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:1575] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 23437 ; free virtual = 49469 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 23478 ; free virtual = 49511 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 23481 ; free virtual = 49515 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 23488 ; free virtual = 49521 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 23512 ; free virtual = 49517 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 23481 ; free virtual = 49487 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 23477 ; free virtual = 49482 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 23469 ; free virtual = 49474 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Loading site data... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading route data... Processing options... Creating bitmap... Loading data files... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:50:41 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2531.891 ; gain = 339.105 ; free physical = 23005 ; free virtual = 49010 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:50:41 2019... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: Launching helper process for spawning children vivado processes --------------------------------------------------------------------------------- INFO: Helper process launched with PID 10045 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 23976 ; free virtual = 49981 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 23966 ; free virtual = 49971 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes touch build/specimen_001/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_002 INFO: Helper process launched with PID 10053 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 23716 ; free virtual = 49721 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:2] INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:13] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:48] INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:53] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:90] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:189] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:63] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:189] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:73] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:387] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:83] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:387] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:486] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:88] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:585] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:108] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:684] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:783] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:118] No constraint files found. WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:783] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:882] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:128] --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:882] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:981] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:138] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:981] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:148] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1179] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:158] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1179] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:163] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1377] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:183] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1476] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:193] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:1575] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:353] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:363] Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 23656 ; free virtual = 49662 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:368] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/top.v:2] INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/top.v:2] --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 23645 ; free virtual = 49651 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 23704 ; free virtual = 49711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 23700 ; free virtual = 49711 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 23681 ; free virtual = 49688 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 23677 ; free virtual = 49685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 23675 ; free virtual = 49682 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 23669 ; free virtual = 49680 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 23669 ; free virtual = 49676 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 23669 ; free virtual = 49676 Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 23664 ; free virtual = 49671 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:25] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000001 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/top.v:2] WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 23655 ; free virtual = 49666 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 23656 ; free virtual = 49667 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 23662 ; free virtual = 49673 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 23674 ; free virtual = 49685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 23682 ; free virtual = 49694 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 23685 ; free virtual = 49696 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 23687 ; free virtual = 49699 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 23691 ; free virtual = 49702 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 23700 ; free virtual = 49712 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 23712 ; free virtual = 49723 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1189.953 ; gain = 94.504 ; free physical = 23789 ; free virtual = 49800 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1197.980 ; gain = 102.531 ; free physical = 23792 ; free virtual = 49803 --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1205.957 ; gain = 110.508 ; free physical = 23805 ; free virtual = 49816 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.926 ; gain = 207.484 ; free physical = 23741 ; free virtual = 49755 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1302.926 ; gain = 207.484 ; free physical = 23732 ; free virtual = 49743 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23725 ; free virtual = 49736 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 23690 ; free virtual = 49701 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 23679 ; free virtual = 49690 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 23671 ; free virtual = 49682 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23630 ; free virtual = 49641 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23629 ; free virtual = 49640 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23628 ; free virtual = 49640 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23628 ; free virtual = 49639 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23626 ; free virtual = 49637 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23626 ; free virtual = 49637 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23624 ; free virtual = 49635 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23619 ; free virtual = 49631 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.910 ; gain = 215.461 ; free physical = 23618 ; free virtual = 49629 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 23563 ; free virtual = 49574 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 23567 ; free virtual = 49579 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 23572 ; free virtual = 49583 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 23574 ; free virtual = 49585 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 23576 ; free virtual = 49587 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 23579 ; free virtual = 49590 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 23582 ; free virtual = 49593 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 23591 ; free virtual = 49602 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 23594 ; free virtual = 49606 INFO: [Project 1-571] Translating synthesized netlist WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:50:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 2451.867 ; gain = 342.105 ; free physical = 23342 ; free virtual = 49354 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:50:47 2019... Loading data files... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_003 Loading site data... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1406.922 ; gain = 324.039 ; free physical = 23938 ; free virtual = 49949 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 23921 ; free virtual = 49932 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Loading route data... Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 23916 ; free virtual = 49927 --------------------------------------------------------------------------------- Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 1401.926 ; gain = 319.039 ; free physical = 23776 ; free virtual = 49787 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Starting Placer Task INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.953 ; gain = 0.000 ; free physical = 23773 ; free virtual = 49784 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1397.680 ; gain = 314.789 ; free physical = 23787 ; free virtual = 49798 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1471.953 ; gain = 0.000 ; free physical = 23804 ; free virtual = 49815 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting Placer Task No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 23794 ; free virtual = 49805 Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.957 ; gain = 0.000 ; free physical = 23794 ; free virtual = 49805 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1465.957 ; gain = 0.000 ; free physical = 23797 ; free virtual = 49808 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 23776 ; free virtual = 49787 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 23768 ; free virtual = 49779 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 23766 ; free virtual = 49777 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 23761 ; free virtual = 49772 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 23757 ; free virtual = 49768 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1339] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:16] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/top.v:2] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 23794 ; free virtual = 49815 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.711 ; gain = 0.000 ; free physical = 23796 ; free virtual = 49817 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1461.711 ; gain = 0.000 ; free physical = 23796 ; free virtual = 49817 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 23797 ; free virtual = 49817 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 23793 ; free virtual = 49813 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 23792 ; free virtual = 49806 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 23799 ; free virtual = 49813 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1327.926 ; gain = 232.477 ; free physical = 23799 ; free virtual = 49813 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 23799 ; free virtual = 49813 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 23798 ; free virtual = 49814 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 23798 ; free virtual = 49814 --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 23797 ; free virtual = 49813 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 23797 ; free virtual = 49814 --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 23797 ; free virtual = 49814 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 23797 ; free virtual = 49814 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 23798 ; free virtual = 49814 --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 23798 ; free virtual = 49815 --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 23800 ; free virtual = 49816 --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 23799 ; free virtual = 49815 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 23798 ; free virtual = 49814 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 23803 ; free virtual = 49815 Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 23803 ; free virtual = 49815 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 23806 ; free virtual = 49818 --------------------------------------------------------------------------------- Creating bitstream... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 23812 ; free virtual = 49824 No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 23816 ; free virtual = 49828 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1327.926 ; gain = 232.477 ; free physical = 23816 ; free virtual = 49828 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 23780 ; free virtual = 49795 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 23765 ; free virtual = 49777 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 23765 ; free virtual = 49777 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 23757 ; free virtual = 49770 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 23683 ; free virtual = 49695 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 23613 ; free virtual = 49625 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 23610 ; free virtual = 49622 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 23608 ; free virtual = 49620 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 23607 ; free virtual = 49619 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 23604 ; free virtual = 49616 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 23604 ; free virtual = 49616 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |SRL16E | 1| |3 |XADC | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 23601 ; free virtual = 49613 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.941 ; gain = 242.492 ; free physical = 23595 ; free virtual = 49607 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1337.949 ; gain = 242.492 ; free physical = 23596 ; free virtual = 49608 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'dut_XADC_X0Y0' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 4 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1398.684 ; gain = 315.797 ; free physical = 23555 ; free virtual = 49571 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Loading site data... 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1405.691 ; gain = 322.797 ; free physical = 23399 ; free virtual = 49416 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads 12 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1420.941 ; gain = 338.047 ; free physical = 23432 ; free virtual = 49448 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 23307 ; free virtual = 49323 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 23307 ; free virtual = 49323 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:50:58 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 2463.434 ; gain = 335.176 ; free physical = 23326 ; free virtual = 49342 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:50:58 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.723 ; gain = 0.000 ; free physical = 23347 ; free virtual = 49363 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1471.723 ; gain = 0.000 ; free physical = 23361 ; free virtual = 49377 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1484.973 ; gain = 0.000 ; free physical = 23393 ; free virtual = 49409 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: c83132f2 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1484.973 ; gain = 0.000 ; free physical = 23393 ; free virtual = 49409 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_004 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 24166 ; free virtual = 50183 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 24079 ; free virtual = 50095 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 24122 ; free virtual = 50138 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 24164 ; free virtual = 50180 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24150 ; free virtual = 50166 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 24151 ; free virtual = 50168 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10438 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 24083 ; free virtual = 50100 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 24082 ; free virtual = 50098 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24081 ; free virtual = 50098 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 24080 ; free virtual = 50097 Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24080 ; free virtual = 50097 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 24079 ; free virtual = 50096 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 24078 ; free virtual = 50095 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 24078 ; free virtual = 50095 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24078 ; free virtual = 50094 --------------------------------------------------------------------------------- Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24078 ; free virtual = 50094 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 24078 ; free virtual = 50094 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24078 ; free virtual = 50094 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24087 ; free virtual = 50103 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24078 ; free virtual = 50094 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 24078 ; free virtual = 50094 Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 24079 ; free virtual = 50096 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 24081 ; free virtual = 50097 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 24080 ; free virtual = 50097 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 23417 ; free virtual = 49433 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1814.445 ; gain = 0.000 ; free physical = 23152 ; free virtual = 49169 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 23025 ; free virtual = 49041 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 23014 ; free virtual = 49031 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 23014 ; free virtual = 49030 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 23013 ; free virtual = 49030 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 23012 ; free virtual = 49029 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 23012 ; free virtual = 49028 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1902.488 ; gain = 500.562 ; free physical = 23011 ; free virtual = 49028 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 22971 ; free virtual = 48988 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Placer Task report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 22955 ; free virtual = 48971 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1d7f8aeb2 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 22949 ; free virtual = 48966 INFO: [Timing 38-35] Done setting XDC timing constraints. Writing bitstream ./design.bit... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.441 ; gain = 0.000 ; free physical = 22743 ; free virtual = 48762 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.199 ; gain = 0.000 ; free physical = 22865 ; free virtual = 48886 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 22892 ; free virtual = 48913 Phase 1.3 Build Placer Netlist Model Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10593 Starting Placer Task Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 22986 ; free virtual = 49007 Phase 1.4 Constrain Clocks/Macros INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting INFO: [Vivado 12-1842] Bitgen Completed Successfully. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 23002 ; free virtual = 49023 INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 23001 ; free virtual = 49022 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1482.738 ; gain = 0.000 ; free physical = 22999 ; free virtual = 49020 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 22995 ; free virtual = 49016 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 22995 ; free virtual = 49016 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.484 ; gain = 519.531 ; free physical = 22992 ; free virtual = 49013 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1991.484 ; gain = 584.562 ; free physical = 22992 ; free virtual = 49013 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 22962 ; free virtual = 48982 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 22925 ; free virtual = 48946 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 22920 ; free virtual = 48941 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 22920 ; free virtual = 48941 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 22920 ; free virtual = 48941 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 22920 ; free virtual = 48941 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.242 ; gain = 470.531 ; free physical = 22921 ; free virtual = 48941 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.242 ; gain = 534.562 ; free physical = 22921 ; free virtual = 48942 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_001/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:51:13 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:03 ; elapsed = 00:00:36 . Memory (MB): peak = 2607.445 ; gain = 389.160 ; free physical = 22724 ; free virtual = 48745 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:51:14 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_001/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_002 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:16] INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1843.203 ; gain = 0.000 ; free physical = 22917 ; free virtual = 48943 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1851.461 ; gain = 0.000 ; free physical = 22749 ; free virtual = 48782 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 22736 ; free virtual = 48763 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1899.211 ; gain = 0.000 ; free physical = 22716 ; free virtual = 48749 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 22713 ; free virtual = 48740 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 22713 ; free virtual = 48740 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd81a835 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1939.504 ; gain = 454.531 ; free physical = 22710 ; free virtual = 48737 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.504 ; gain = 454.531 ; free physical = 22706 ; free virtual = 48733 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.504 ; gain = 454.531 ; free physical = 22706 ; free virtual = 48733 Phase 1 Placer Initialization | Checksum: 1373fb29f Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1939.504 ; gain = 454.531 ; free physical = 22706 ; free virtual = 48733 Phase 2 Global Placement Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.254 ; gain = 515.531 ; free physical = 22706 ; free virtual = 48733 Phase 1.3 Build Placer Netlist Model Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 22702 ; free virtual = 48729 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.254 ; gain = 515.531 ; free physical = 22700 ; free virtual = 48727 Phase 1.4 Constrain Clocks/Macros Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 22699 ; free virtual = 48726 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 22699 ; free virtual = 48726 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 22699 ; free virtual = 48725 Phase 2 Final Placement Cleanup Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.254 ; gain = 515.531 ; free physical = 22697 ; free virtual = 48723 Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 22696 ; free virtual = 48723 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.246 ; gain = 467.531 ; free physical = 22696 ; free virtual = 48723 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.246 ; gain = 532.562 ; free physical = 22696 ; free virtual = 48723 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.254 ; gain = 515.531 ; free physical = 22695 ; free virtual = 48722 Phase 2 Final Placement Cleanup INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.254 ; gain = 515.531 ; free physical = 22693 ; free virtual = 48719 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.254 ; gain = 515.531 ; free physical = 22690 ; free virtual = 48717 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.254 ; gain = 581.562 ; free physical = 22689 ; free virtual = 48715 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 22492 ; free virtual = 48519 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 22274 ; free virtual = 48301 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11489 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/top.v:2] Phase 2 Global Placement | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22263 ; free virtual = 48290 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1ba0d5f8c Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22265 ; free virtual = 48292 Phase 3.2 Commit Most Macros & LUTRAMs --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 22274 ; free virtual = 48301 --------------------------------------------------------------------------------- Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 16b25666e Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22275 ; free virtual = 48302 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1dee41518 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22260 ; free virtual = 48288 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 175ba2c6b Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22260 ; free virtual = 48287 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 22227 ; free virtual = 48255 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 22225 ; free virtual = 48252 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 22242 ; free virtual = 48269 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 3.5 Small Shape Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22213 ; free virtual = 48240 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22213 ; free virtual = 48240 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22213 ; free virtual = 48240 Phase 3 Detail Placement | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22212 ; free virtual = 48239 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22210 ; free virtual = 48237 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22207 ; free virtual = 48234 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22207 ; free virtual = 48234 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22206 ; free virtual = 48233 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1573cf0c4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22206 ; free virtual = 48233 Ending Placer Task | Checksum: 584e5438 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2035.551 ; gain = 550.578 ; free physical = 22218 ; free virtual = 48245 22 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2035.551 ; gain = 614.609 ; free physical = 22218 ; free virtual = 48245 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 248660b8 ConstDB: 0 ShapeSum: 33c7f380 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 21880 ; free virtual = 47907 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 21767 ; free virtual = 47794 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21440 ; free virtual = 47467 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 21431 ; free virtual = 47458 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21344 ; free virtual = 47371 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21336 ; free virtual = 47363 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1ddcd7ec8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 21316 ; free virtual = 47343 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21303 ; free virtual = 47330 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 2751fe4ae Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 21300 ; free virtual = 47327 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21295 ; free virtual = 47322 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 2751fe4ae Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 21288 ; free virtual = 47315 --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21285 ; free virtual = 47312 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21280 ; free virtual = 47307 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | Phase 1 Placer Initialization | Checksum: 2751fe4ae +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 21279 ; free virtual = 47306 Phase 2 Global Placement Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21277 ; free virtual = 47305 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21259 ; free virtual = 47286 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 21257 ; free virtual = 47284 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 21043 ; free virtual = 47070 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.227 ; gain = 0.000 ; free physical = 21037 ; free virtual = 47064 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 21025 ; free virtual = 47052 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21011 ; free virtual = 47038 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 20921 ; free virtual = 46948 Phase 1.3 Build Placer Netlist Model Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 20922 ; free virtual = 46949 --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 20921 ; free virtual = 46948 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 20920 ; free virtual = 46947 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 20994 ; free virtual = 47021 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 20993 ; free virtual = 47020 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1994.270 ; gain = 511.531 ; free physical = 20978 ; free virtual = 47005 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 577.562 ; free physical = 20978 ; free virtual = 47005 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20899 ; free virtual = 46926 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20898 ; free virtual = 46925 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20898 ; free virtual = 46925 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20898 ; free virtual = 46925 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20898 ; free virtual = 46925 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20898 ; free virtual = 46925 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20897 ; free virtual = 46924 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20897 ; free virtual = 46924 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20895 ; free virtual = 46922 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:19] INFO: [Synth 8-638] synthesizing module 'ICAPE2' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] Parameter DEVICE_ID bound to: 56955027 - type: integer Parameter ICAP_WIDTH bound to: X32 - type: string Parameter SIM_CFG_FILE_NAME bound to: NONE - type: string INFO: [Synth 8-256] done synthesizing module 'ICAPE2' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16247] WARNING: [Synth 8-350] instance 'icap_ICAP_X0Y1' of module 'ICAPE2' requires 5 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:19] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/top.v:2] Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 2 Global Placement | Checksum: 26d08ed71 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20789 ; free virtual = 46818 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26d08ed71 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20792 ; free virtual = 46820 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 20d0b931e Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20803 ; free virtual = 46830 Phase 3.3 Area Swap Optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 20813 ; free virtual = 46841 --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 1e6e670e9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20812 ; free virtual = 46840 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1b09ad14e Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20812 ; free virtual = 46840 Phase 3.5 Small Shape Detail Placement --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 20806 ; free virtual = 46834 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 20805 ; free virtual = 46833 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 20805 ; free virtual = 46833 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 3.5 Small Shape Detail Placement | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20779 ; free virtual = 46807 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20776 ; free virtual = 46804 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20773 ; free virtual = 46801 Phase 3 Detail Placement | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20772 ; free virtual = 46800 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20767 ; free virtual = 46795 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21178465f Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20763 ; free virtual = 46791 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20760 ; free virtual = 46788 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20758 ; free virtual = 46786 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21178465f Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20756 ; free virtual = 46784 Ending Placer Task | Checksum: 1c94b2d26 Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.543 ; gain = 595.574 ; free physical = 20768 ; free virtual = 46795 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.543 ; gain = 659.605 ; free physical = 20767 ; free virtual = 46795 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e4ab841c ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1396.684 ; gain = 313.797 ; free physical = 20555 ; free virtual = 46582 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 20537 ; free virtual = 46565 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1460.715 ; gain = 0.000 ; free physical = 20537 ; free virtual = 46565 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 1468.250 ; gain = 385.359 ; free physical = 20392 ; free virtual = 46419 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 20218 ; free virtual = 46246 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1545.281 ; gain = 0.000 ; free physical = 20236 ; free virtual = 46264 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: Launching helper process for spawning children vivado processes No constraint files found. INFO: Helper process launched with PID 12445 --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 20232 ; free virtual = 46260 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20230 ; free virtual = 46258 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1545.281 ; gain = 0.000 ; free physical = 20213 ; free virtual = 46240 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20124 ; free virtual = 46178 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20123 ; free virtual = 46177 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20123 ; free virtual = 46177 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20123 ; free virtual = 46177 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20123 ; free virtual = 46177 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20123 ; free virtual = 46177 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |ICAPE2 | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20122 ; free virtual = 46177 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20122 ; free virtual = 46176 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 20124 ; free virtual = 46178 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1396.688 ; gain = 313.797 ; free physical = 19947 ; free virtual = 46035 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 19905 ; free virtual = 45994 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3a62fa46 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1460.719 ; gain = 0.000 ; free physical = 19905 ; free virtual = 45994 Phase 1 Build RT Design | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2054.172 ; gain = 119.668 ; free physical = 19857 ; free virtual = 45946 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2059.160 ; gain = 124.656 ; free physical = 19825 ; free virtual = 45913 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2059.160 ; gain = 124.656 ; free physical = 19825 ; free virtual = 45913 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19815 ; free virtual = 45903 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19817 ; free virtual = 45905 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19815 ; free virtual = 45903 Phase 4 Rip-up And Reroute | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19815 ; free virtual = 45903 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19815 ; free virtual = 45903 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19815 ; free virtual = 45903 Phase 6 Post Hold Fix | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19815 ; free virtual = 45903 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19806 ; free virtual = 45895 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.215 ; gain = 133.711 ; free physical = 19805 ; free virtual = 45893 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.215 ; gain = 133.711 ; free physical = 19805 ; free virtual = 45893 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.215 ; gain = 133.711 ; free physical = 19837 ; free virtual = 45925 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2107.004 ; gain = 204.516 ; free physical = 19836 ; free virtual = 45925 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2107.004 ; gain = 0.000 ; free physical = 19819 ; free virtual = 45909 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.559 ; gain = 81.648 ; free physical = 19802 ; free virtual = 45891 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 1610a2161 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2057.926 ; gain = 93.668 ; free physical = 19785 ; free virtual = 45873 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1610a2161 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2062.914 ; gain = 98.656 ; free physical = 19753 ; free virtual = 45841 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1610a2161 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2062.914 ; gain = 98.656 ; free physical = 19752 ; free virtual = 45841 Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.168 ; gain = 44.668 ; free physical = 19739 ; free virtual = 45828 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2074.156 ; gain = 50.656 ; free physical = 19709 ; free virtual = 45797 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2074.156 ; gain = 50.656 ; free physical = 19708 ; free virtual = 45797 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f655770e Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 19691 ; free virtual = 45780 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 19664 ; free virtual = 45753 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 19652 ; free virtual = 45740 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 19646 ; free virtual = 45734 Phase 4 Rip-up And Reroute | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 19646 ; free virtual = 45734 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 19646 ; free virtual = 45734 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 19646 ; free virtual = 45734 Phase 6 Post Hold Fix | Checksum: f655770e Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.969 ; gain = 104.711 ; free physical = 19645 ; free virtual = 45734 Phase 7 Route finalize Number of Nodes with overlaps = 0 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 19678 ; free virtual = 45766 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2] Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 19679 ; free virtual = 45768 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 19678 ; free virtual = 45767 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 19678 ; free virtual = 45767 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 19677 ; free virtual = 45765 Phase 7 Route finalize | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.969 ; gain = 105.711 ; free physical = 19677 ; free virtual = 45765 Phase 8 Verifying routed nets Verification completed successfully Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.461 ; gain = 61.961 ; free physical = 19675 ; free virtual = 45764 Phase 8 Verifying routed nets | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2072.969 ; gain = 108.711 ; free physical = 19675 ; free virtual = 45764 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f655770e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2072.969 ; gain = 108.711 ; free physical = 19674 ; free virtual = 45762 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2072.969 ; gain = 108.711 ; free physical = 19707 ; free virtual = 45795 Routing Is Done. Phase 7 Route finalize 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2111.758 ; gain = 179.516 ; free physical = 19703 ; free virtual = 45791 INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:24] Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1416] Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1584] Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.461 ; gain = 62.961 ; free physical = 19686 ; free virtual = 45775 Phase 8 Verifying routed nets WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1800] Verification completed successfully WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1848] Writing placer database... WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1944] Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.461 ; gain = 65.961 ; free physical = 19682 ; free virtual = 45771 Phase 9 Depositing Routes Writing XDEF routing. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2111.758 ; gain = 0.000 ; free physical = 19683 ; free virtual = 45773 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.461 ; gain = 65.961 ; free physical = 19685 ; free virtual = 45774 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.461 ; gain = 65.961 ; free physical = 19725 ; free virtual = 45814 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2128.250 ; gain = 136.766 ; free physical = 19725 ; free virtual = 45814 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2128.250 ; gain = 0.000 ; free physical = 19588 ; free virtual = 45681 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.203 ; gain = 0.000 ; free physical = 19295 ; free virtual = 45385 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 19315 ; free virtual = 45405 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 19308 ; free virtual = 45398 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 19308 ; free virtual = 45398 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 19308 ; free virtual = 45398 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 19308 ; free virtual = 45398 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 443.531 ; free physical = 19309 ; free virtual = 45398 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.246 ; gain = 507.562 ; free physical = 19309 ; free virtual = 45398 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Phase 1 Build RT Design | Checksum: dc8ba1ed Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2055.930 ; gain = 92.668 ; free physical = 18792 ; free virtual = 44882 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: dc8ba1ed Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2060.918 ; gain = 97.656 ; free physical = 18734 ; free virtual = 44823 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: dc8ba1ed Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2060.918 ; gain = 97.656 ; free physical = 18733 ; free virtual = 44823 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 927a5c4b Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 18551 ; free virtual = 44640 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 18490 ; free virtual = 44579 Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2063.938 ; gain = 44.668 ; free physical = 18487 ; free virtual = 44577 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 18487 ; free virtual = 44576 Phase 4 Rip-up And Reroute | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 18487 ; free virtual = 44576 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 18487 ; free virtual = 44576 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 18487 ; free virtual = 44576 Phase 6 Post Hold Fix | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.973 ; gain = 104.711 ; free physical = 18487 ; free virtual = 44576 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.926 ; gain = 50.656 ; free physical = 18442 ; free virtual = 44531 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.926 ; gain = 50.656 ; free physical = 18442 ; free virtual = 44531 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 7 Route finalize | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.973 ; gain = 105.711 ; free physical = 18435 ; free virtual = 44524 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2071.973 ; gain = 108.711 ; free physical = 18433 ; free virtual = 44523 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 927a5c4b Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2071.973 ; gain = 108.711 ; free physical = 18433 ; free virtual = 44522 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2071.973 ; gain = 108.711 ; free physical = 18466 ; free virtual = 44555 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2110.762 ; gain = 179.516 ; free physical = 18465 ; free virtual = 44555 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 18452 ; free virtual = 44543 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2079.980 ; gain = 60.711 ; free physical = 18443 ; free virtual = 44533 Phase 3 Initial Routing Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.770 ; gain = 0.000 ; free physical = 18443 ; free virtual = 44533 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.980 ; gain = 62.711 ; free physical = 18347 ; free virtual = 44437 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.980 ; gain = 62.711 ; free physical = 18323 ; free virtual = 44413 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.980 ; gain = 62.711 ; free physical = 18316 ; free virtual = 44406 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.980 ; gain = 62.711 ; free physical = 18317 ; free virtual = 44407 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.980 ; gain = 62.711 ; free physical = 18318 ; free virtual = 44408 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.980 ; gain = 62.711 ; free physical = 18319 ; free virtual = 44409 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2081.980 ; gain = 62.711 ; free physical = 18319 ; free virtual = 44409 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2083.980 ; gain = 64.711 ; free physical = 18325 ; free virtual = 44415 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2083.980 ; gain = 64.711 ; free physical = 18337 ; free virtual = 44426 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2083.980 ; gain = 64.711 ; free physical = 18373 ; free virtual = 44462 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2122.770 ; gain = 135.516 ; free physical = 18372 ; free virtual = 44462 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2122.770 ; gain = 0.000 ; free physical = 18334 ; free virtual = 44426 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2003.484 ; gain = 458.203 ; free physical = 18233 ; free virtual = 44323 Phase 1.3 Build Placer Netlist Model Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 1501539a8 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2071.191 ; gain = 35.641 ; free physical = 18123 ; free virtual = 44213 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1501539a8 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2075.180 ; gain = 39.629 ; free physical = 18039 ; free virtual = 44129 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1501539a8 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2075.180 ; gain = 39.629 ; free physical = 18036 ; free virtual = 44127 INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/top.v:2] Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: d17cc5cd Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 17959 ; free virtual = 44057 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 17898 ; free virtual = 44007 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 17879 ; free virtual = 43989 Phase 4 Rip-up And Reroute | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 17879 ; free virtual = 43989 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 17879 ; free virtual = 43989 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 17878 ; free virtual = 43988 Phase 6 Post Hold Fix | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 17877 ; free virtual = 43987 Phase 7 Route finalize WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 17832 ; free virtual = 43943 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 17831 ; free virtual = 43941 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1446381a7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 17829 ; free virtual = 43940 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2096.234 ; gain = 60.684 ; free physical = 17859 ; free virtual = 43970 Routing Is Done. 29 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2135.023 ; gain = 99.473 ; free physical = 17856 ; free virtual = 43967 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2135.023 ; gain = 0.000 ; free physical = 17812 ; free virtual = 43925 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 17812 ; free virtual = 43905 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... Loading route data... Processing options... Creating bitmap... Loading data files... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.484 ; gain = 458.203 ; free physical = 17538 ; free virtual = 43650 Phase 1.4 Constrain Clocks/Macros Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.484 ; gain = 458.203 ; free physical = 17495 ; free virtual = 43607 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1816.207 ; gain = 0.000 ; free physical = 17458 ; free virtual = 43570 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.484 ; gain = 458.203 ; free physical = 17447 ; free virtual = 43558 Phase 2 Global Placement --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 17448 ; free virtual = 43540 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1334.094 ; gain = 238.184 ; free physical = 17442 ; free virtual = 43534 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 17417 ; free virtual = 43509 Phase 1.3 Build Placer Netlist Model INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1.3 Build Placer Netlist Model | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 17428 ; free virtual = 43520 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 17428 ; free virtual = 43520 Phase 1 Placer Initialization | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 17428 ; free virtual = 43520 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 9076bb26 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 17429 ; free virtual = 43521 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 3a62fa46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 443.531 ; free physical = 17431 ; free virtual = 43523 21 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1904.250 ; gain = 507.562 ; free physical = 17432 ; free virtual = 43524 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Loading site data... Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 3a62fa46 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading route data... Processing options... Creating bitmap... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Loading site data... Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:26 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 17042 ; free virtual = 43134 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Loading route data... Processing options... Creating bitmap... Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 16977 ; free virtual = 43069 Phase 3.2 Commit Most Macros & LUTRAMs Creating bitstream... Writing bitstream ./design.bit... Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 16916 ; free virtual = 43009 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 16961 ; free virtual = 43057 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 17048 ; free virtual = 43145 Phase 3.5 Small Shape Detail Placement INFO: [Vivado 12-1842] Bitgen Completed Successfully. Loading data files... INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: d6a1f794 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.953 ; gain = 41.668 ; free physical = 17086 ; free virtual = 43182 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: d6a1f794 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 17056 ; free virtual = 43153 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: d6a1f794 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 17057 ; free virtual = 43153 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 1345.062 ; gain = 249.152 ; free physical = 17054 ; free virtual = 43150 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 17039 ; free virtual = 43135 Phase 3.6 Re-assign LUT pins Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b1023f3e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.246 ; gain = 59.961 ; free physical = 17033 ; free virtual = 43129 Phase 3 Initial Routing Writing bitstream ./design.bit... Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 17024 ; free virtual = 43121 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 17016 ; free virtual = 43116 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 17039 ; free virtual = 43139 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 17059 ; free virtual = 43159 Phase 4 Rip-up And Reroute | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 17069 ; free virtual = 43169 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 17071 ; free virtual = 43171 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 17072 ; free virtual = 43172 Phase 6 Post Hold Fix | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 17073 ; free virtual = 43174 Phase 7 Route finalize Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 17124 ; free virtual = 43224 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.246 ; gain = 62.961 ; free physical = 17281 ; free virtual = 43381 Phase 8 Verifying routed nets Verification completed successfully INFO: [Vivado 12-1842] Bitgen Completed Successfully. Phase 8 Verifying routed nets | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 17292 ; free virtual = 43392 Phase 9 Depositing Routes INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 17281 ; free virtual = 43381 Phase 4.2 Post Placement Cleanup Phase 9 Depositing Routes | Checksum: 1b1023f3e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 17281 ; free virtual = 43381 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.246 ; gain = 64.961 ; free physical = 17317 ; free virtual = 43418 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2130.035 ; gain = 135.766 ; free physical = 17316 ; free virtual = 43416 Writing placer database... Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 17299 ; free virtual = 43400 Phase 4.3 Placer Reporting Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 17294 ; free virtual = 43397 Phase 4.4 Final Placement Cleanup Write XDEF Complete: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2130.035 ; gain = 0.000 ; free physical = 17293 ; free virtual = 43397 Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 17281 ; free virtual = 43391 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 17245 ; free virtual = 43346 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.531 ; gain = 554.250 ; free physical = 17184 ; free virtual = 43285 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.531 ; gain = 631.281 ; free physical = 17181 ; free virtual = 43282 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 13eb18239 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 17137 ; free virtual = 43238 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 13eb18239 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 17102 ; free virtual = 43203 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 13eb18239 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2084.543 ; gain = 0.000 ; free physical = 17102 ; free virtual = 43203 Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:52:16 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 2451.109 ; gain = 344.105 ; free physical = 17079 ; free virtual = 43181 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:52:16 2019... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 1353.094 ; gain = 257.184 ; free physical = 17230 ; free virtual = 43335 --------------------------------------------------------------------------------- Loading site data... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_003 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 12e953610 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2100.230 ; gain = 15.688 ; free physical = 18312 ; free virtual = 44417 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 1353.094 ; gain = 257.184 ; free physical = 18323 ; free virtual = 44428 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2100.230 ; gain = 15.688 ; free physical = 18254 ; free virtual = 44359 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2100.230 ; gain = 15.688 ; free physical = 18248 ; free virtual = 44353 Phase 4 Rip-up And Reroute | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2100.230 ; gain = 15.688 ; free physical = 18247 ; free virtual = 44352 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2100.230 ; gain = 15.688 ; free physical = 18244 ; free virtual = 44349 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2100.230 ; gain = 15.688 ; free physical = 18242 ; free virtual = 44347 Phase 6 Post Hold Fix | Checksum: b2ce332f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2100.230 ; gain = 15.688 ; free physical = 18241 ; free virtual = 44346 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2100.230 ; gain = 15.688 ; free physical = 18216 ; free virtual = 44321 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2100.230 ; gain = 15.688 ; free physical = 18212 ; free virtual = 44317 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: b2ce332f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2100.230 ; gain = 15.688 ; free physical = 18198 ; free virtual = 44303 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2100.230 ; gain = 15.688 ; free physical = 18230 ; free virtual = 44335 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2139.020 ; gain = 54.477 ; free physical = 18227 ; free virtual = 44332 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:52:18 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2453.863 ; gain = 342.105 ; free physical = 18204 ; free virtual = 44311 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:52:18 2019... Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2139.020 ; gain = 0.000 ; free physical = 18207 ; free virtual = 44314 Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:37 . Memory (MB): peak = 1361.070 ; gain = 265.160 ; free physical = 19140 ; free virtual = 45245 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Loading route data... --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Processing options... Creating bitmap... Creating bitstream... touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dframe 15 --dword 0" bash ../fuzzaddr/generate.sh build/specimen_004 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:52:20 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2472.355 ; gain = 344.105 ; free physical = 19079 ; free virtual = 45185 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:52:20 2019... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1361.070 ; gain = 265.160 ; free physical = 19340 ; free virtual = 45445 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1361.070 ; gain = 265.160 ; free physical = 20061 ; free virtual = 46166 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Number of configuration frames: 9996 --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- DONE touch build/specimen_003/OK --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1361.070 ; gain = 265.160 ; free physical = 19986 ; free virtual = 46091 GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_004 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1361.070 ; gain = 265.160 ; free physical = 20020 ; free virtual = 46125 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1361.070 ; gain = 265.160 ; free physical = 20017 ; free virtual = 46123 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1361.070 ; gain = 265.160 ; free physical = 20010 ; free virtual = 46115 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1361.070 ; gain = 265.160 ; free physical = 20009 ; free virtual = 46114 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1361.070 ; gain = 265.160 ; free physical = 20008 ; free virtual = 46113 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1361.078 ; gain = 265.160 ; free physical = 20012 ; free virtual = 46117 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Project 1-571] Translating synthesized netlist Loading data files... Writing bitstream ./design.bit... Loading site data... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading route data... Processing options... Creating bitmap... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Creating bitstream... Loading data files... Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:52:26 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2453.867 ; gain = 343.105 ; free physical = 19920 ; free virtual = 46030 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:52:26 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Netlist 29-28] Unisim Transformation completed in 3 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:52:31 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 39 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 2468.129 ; gain = 333.105 ; free physical = 21048 ; free virtual = 47166 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:52:31 2019... Bitstream size: 4243411 bytes Config size: 1060815 words INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:52:32 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Number of configuration frames: 9996 DONE 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:29 . Memory (MB): peak = 2461.875 ; gain = 339.105 ; free physical = 22029 ; free virtual = 48147 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:52:32 2019... touch build/specimen_002/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. #of segments: 2 #of bits: 388 #of tags: 1 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_003 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_003 Loading site data... Loading route data... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1 Build RT Design | Checksum: c47cd168 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2054.930 ; gain = 118.668 ; free physical = 22637 ; free virtual = 48757 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: c47cd168 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2060.918 ; gain = 124.656 ; free physical = 22589 ; free virtual = 48708 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: c47cd168 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2060.918 ; gain = 124.656 ; free physical = 22586 ; free virtual = 48706 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 22565 ; free virtual = 48684 Phase 3 Initial Routing INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 22467 ; free virtual = 48587 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 22455 ; free virtual = 48574 Phase 4 Rip-up And Reroute | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 22454 ; free virtual = 48574 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 22454 ; free virtual = 48573 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 22454 ; free virtual = 48573 Phase 6 Post Hold Fix | Checksum: 1481dbb17 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.973 ; gain = 131.711 ; free physical = 22453 ; free virtual = 48573 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.973 ; gain = 132.711 ; free physical = 22421 ; free virtual = 48540 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.973 ; gain = 134.711 ; free physical = 22435 ; free virtual = 48554 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1481dbb17 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.973 ; gain = 134.711 ; free physical = 22457 ; free virtual = 48577 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.973 ; gain = 134.711 ; free physical = 22529 ; free virtual = 48649 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2109.762 ; gain = 205.516 ; free physical = 22552 ; free virtual = 48671 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13962 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2109.762 ; gain = 0.000 ; free physical = 22542 ; free virtual = 48662 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Writing bitstream ./design.bit... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14012 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14068 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:04 . Memory (MB): peak = 1476.820 ; gain = 393.938 ; free physical = 22936 ; free virtual = 49063 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:52:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:30 . Memory (MB): peak = 2469.141 ; gain = 339.105 ; free physical = 22784 ; free virtual = 48912 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:52:45 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1554.852 ; gain = 0.000 ; free physical = 23656 ; free virtual = 49785 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.41 . Memory (MB): peak = 1554.852 ; gain = 0.000 ; free physical = 23617 ; free virtual = 49746 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:52:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2474.125 ; gain = 335.105 ; free physical = 23594 ; free virtual = 49724 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:52:47 2019... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14196 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_003 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 24491 ; free virtual = 50621 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 109653c4d Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2055.934 ; gain = 119.668 ; free physical = 24471 ; free virtual = 50601 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 109653c4d Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2060.922 ; gain = 124.656 ; free physical = 24418 ; free virtual = 50549 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 109653c4d Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 2060.922 ; gain = 124.656 ; free physical = 24417 ; free virtual = 50548 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 116fd9d52 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 24357 ; free virtual = 50487 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 24367 ; free virtual = 50497 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 24340 ; free virtual = 50470 Phase 4 Rip-up And Reroute | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 24338 ; free virtual = 50468 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 24337 ; free virtual = 50467 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 24338 ; free virtual = 50468 Phase 6 Post Hold Fix | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 24353 ; free virtual = 50483 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.977 ; gain = 131.711 ; free physical = 24337 ; free virtual = 50468 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 24336 ; free virtual = 50466 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 116fd9d52 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 24335 ; free virtual = 50465 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.977 ; gain = 133.711 ; free physical = 24368 ; free virtual = 50498 Routing Is Done. 28 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2108.766 ; gain = 204.516 ; free physical = 24368 ; free virtual = 50498 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2108.766 ; gain = 0.000 ; free physical = 24355 ; free virtual = 50487 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 24271 ; free virtual = 50402 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 24269 ; free virtual = 50400 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1189.949 ; gain = 94.504 ; free physical = 24281 ; free virtual = 50412 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 24281 ; free virtual = 50412 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1197.977 ; gain = 102.531 ; free physical = 24296 ; free virtual = 50427 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:16] INFO: [Synth 8-638] synthesizing module 'XADC' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] Parameter INIT_40 bound to: 16'b0000000000000000 Parameter INIT_41 bound to: 16'b0000000000000000 Parameter INIT_42 bound to: 16'b0000100000000000 Parameter INIT_43 bound to: 16'b0000000000000000 Parameter INIT_44 bound to: 16'b0000000000000000 Parameter INIT_45 bound to: 16'b0000000000000000 Parameter INIT_46 bound to: 16'b0000000000000000 Parameter INIT_47 bound to: 16'b0000000000000000 Parameter INIT_48 bound to: 16'b0000000000000000 Parameter INIT_49 bound to: 16'b0000000000000000 Parameter INIT_4A bound to: 16'b0000000000000000 Parameter INIT_4B bound to: 16'b0000000000000000 Parameter INIT_4C bound to: 16'b0000000000000000 Parameter INIT_4D bound to: 16'b0000000000000000 Parameter INIT_4E bound to: 16'b0000000000000000 Parameter INIT_4F bound to: 16'b0000000000000000 Parameter INIT_50 bound to: 16'b0000000000000000 Parameter INIT_51 bound to: 16'b0000000000000000 Parameter INIT_52 bound to: 16'b0000000000000000 Parameter INIT_53 bound to: 16'b0000000000000000 Parameter INIT_54 bound to: 16'b0000000000000000 Parameter INIT_55 bound to: 16'b0000000000000000 Parameter INIT_56 bound to: 16'b0000000000000000 Parameter INIT_57 bound to: 16'b0000000000000000 Parameter INIT_58 bound to: 16'b0000000000000000 Parameter INIT_59 bound to: 16'b0000000000000000 Parameter INIT_5A bound to: 16'b0000000000000000 Parameter INIT_5B bound to: 16'b0000000000000000 Parameter INIT_5C bound to: 16'b0000000000000000 Parameter INIT_5D bound to: 16'b0000000000000000 Parameter INIT_5E bound to: 16'b0000000000000000 Parameter INIT_5F bound to: 16'b0000000000000000 Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 Parameter IS_DCLK_INVERTED bound to: 1'b0 Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SIM_MONITOR_FILE bound to: design.txt - type: string INFO: [Synth 8-256] done synthesizing module 'XADC' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:45495] WARNING: [Synth 8-350] instance 'xadc' of module 'XADC' requires 24 connections, but only 3 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:16] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 24196 ; free virtual = 50327 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 24203 ; free virtual = 50334 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1189.945 ; gain = 94.504 ; free physical = 24183 ; free virtual = 50314 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 24181 ; free virtual = 50312 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1197.973 ; gain = 102.531 ; free physical = 24169 ; free virtual = 50300 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading site data... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:120] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:575] Loading route data... WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:582] Processing options... WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:638] Creating bitmap... WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 23891 ; free virtual = 50022 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14307 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 23832 ; free virtual = 49963 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 23853 ; free virtual = 49984 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 23834 ; free virtual = 49965 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14343 Loading data files... Creating bitstream... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 23629 ; free virtual = 49761 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 23569 ; free virtual = 49705 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 23729 ; free virtual = 49865 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 23734 ; free virtual = 49870 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 23714 ; free virtual = 49850 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:38 . Memory (MB): peak = 2130.289 ; gain = 30.758 ; free physical = 23682 ; free virtual = 49818 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:38 . Memory (MB): peak = 2135.277 ; gain = 35.746 ; free physical = 23616 ; free virtual = 49752 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:38 . Memory (MB): peak = 2135.277 ; gain = 35.746 ; free physical = 23615 ; free virtual = 49751 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 23601 ; free virtual = 49737 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 23565 ; free virtual = 49701 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 23622 ; free virtual = 49758 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2154.332 ; gain = 54.801 ; free physical = 23594 ; free virtual = 49730 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2154.332 ; gain = 54.801 ; free physical = 23555 ; free virtual = 49691 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2154.332 ; gain = 54.801 ; free physical = 23554 ; free virtual = 49690 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2154.332 ; gain = 54.801 ; free physical = 23554 ; free virtual = 49690 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2154.332 ; gain = 54.801 ; free physical = 23554 ; free virtual = 49690 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2154.332 ; gain = 54.801 ; free physical = 23554 ; free virtual = 49690 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2154.332 ; gain = 54.801 ; free physical = 23554 ; free virtual = 49690 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:39 . Memory (MB): peak = 2154.332 ; gain = 54.801 ; free physical = 23547 ; free virtual = 49683 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:39 . Memory (MB): peak = 2154.332 ; gain = 54.801 ; free physical = 23546 ; free virtual = 49681 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:39 . Memory (MB): peak = 2154.332 ; gain = 54.801 ; free physical = 23546 ; free virtual = 49681 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:39 . Memory (MB): peak = 2154.332 ; gain = 54.801 ; free physical = 23581 ; free virtual = 49716 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:42 . Memory (MB): peak = 2193.121 ; gain = 93.590 ; free physical = 23581 ; free virtual = 49717 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 23580 ; free virtual = 49716 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 23577 ; free virtual = 49713 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 23576 ; free virtual = 49712 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 23576 ; free virtual = 49712 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 23576 ; free virtual = 49711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 23575 ; free virtual = 49711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 23574 ; free virtual = 49710 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 23572 ; free virtual = 49708 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 23574 ; free virtual = 49710 Writing placer database... INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1302.926 ; gain = 207.484 ; free physical = 23445 ; free virtual = 49585 --------------------------------------------------------------------------------- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1302.926 ; gain = 207.484 ; free physical = 23431 ; free virtual = 49572 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23442 ; free virtual = 49584 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:52:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2450.867 ; gain = 341.105 ; free physical = 23418 ; free virtual = 49564 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:52:59 2019... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23505 ; free virtual = 49652 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23505 ; free virtual = 49652 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23522 ; free virtual = 49670 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23584 ; free virtual = 49732 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23660 ; free virtual = 49808 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23684 ; free virtual = 49833 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-----+------+ | |Cell |Count | +------+-----+------+ |1 |XADC | 1| +------+-----+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 1| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 23742 ; free virtual = 49890 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.902 ; gain = 215.461 ; free physical = 24009 ; free virtual = 50157 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.910 ; gain = 215.461 ; free physical = 24080 ; free virtual = 50229 INFO: [Project 1-571] Translating synthesized netlist Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_004 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Netlist 29-345] The value of SIM_DEVICE on instance 'xadc' of type 'XADC' is '7SERIES'; it is being changed to match the current FPGA architecture, 'ZYNQ'. For functional simulation to match hardware behavior, the value of SIM_DEVICE should be changed in the source netlist. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 24204 ; free virtual = 50357 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 24184 ; free virtual = 50338 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 24164 ; free virtual = 50318 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 24157 ; free virtual = 50314 --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.121 ; gain = 0.000 ; free physical = 24165 ; free virtual = 50323 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 23979 ; free virtual = 50116 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 23964 ; free virtual = 50101 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 23941 ; free virtual = 50078 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 23940 ; free virtual = 50077 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 23938 ; free virtual = 50075 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 23948 ; free virtual = 50085 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 23938 ; free virtual = 50075 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 23932 ; free virtual = 50069 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 23952 ; free virtual = 50089 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 23950 ; free virtual = 50087 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Loading site data... 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1401.688 ; gain = 318.797 ; free physical = 23821 ; free virtual = 49958 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:328] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Loading route data... Processing options... Running DRC as a precondition to command write_bitstream Creating bitmap... INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/top.v:2] Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 23638 ; free virtual = 49775 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1465.719 ; gain = 0.000 ; free physical = 23637 ; free virtual = 49774 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 23567 ; free virtual = 49705 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 23536 ; free virtual = 49673 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 23534 ; free virtual = 49672 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 23521 ; free virtual = 49658 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 12 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1401.926 ; gain = 319.039 ; free physical = 23493 ; free virtual = 49631 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 23486 ; free virtual = 49623 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 23471 ; free virtual = 49609 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.340 ; gain = 0.000 ; free physical = 23471 ; free virtual = 49608 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 23476 ; free virtual = 49614 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Starting Placer Task Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1465.957 ; gain = 0.000 ; free physical = 23454 ; free virtual = 49592 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: b3fd8609 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1465.957 ; gain = 0.000 ; free physical = 23454 ; free virtual = 49592 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14532 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 23336 ; free virtual = 49474 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 23334 ; free virtual = 49472 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 23329 ; free virtual = 49467 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 23327 ; free virtual = 49465 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 23325 ; free virtual = 49463 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 23323 ; free virtual = 49461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 23321 ; free virtual = 49458 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 23313 ; free virtual = 49450 Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 23313 ; free virtual = 49450 INFO: [Project 1-571] Translating synthesized netlist ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing bitstream ./design.bit... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2052.383 ; gain = 497.531 ; free physical = 23177 ; free virtual = 49318 Phase 1.3 Build Placer Netlist Model INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 23436 ; free virtual = 49578 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:16] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14626 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/top.v:2] Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.961 ; gain = 0.000 ; free physical = 23387 ; free virtual = 49535 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1470.961 ; gain = 0.000 ; free physical = 23382 ; free virtual = 49530 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 23378 ; free virtual = 49520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 23286 ; free virtual = 49428 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 23284 ; free virtual = 49427 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1397.691 ; gain = 314.797 ; free physical = 23154 ; free virtual = 49296 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 23116 ; free virtual = 49258 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:53:09 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 38 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2451.871 ; gain = 343.105 ; free physical = 23116 ; free virtual = 49258 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.383 ; gain = 497.531 ; free physical = 23116 ; free virtual = 49258 Phase 1.4 Constrain Clocks/Macros INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:53:09 2019... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 23124 ; free virtual = 49266 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 23129 ; free virtual = 49271 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.383 ; gain = 497.531 ; free physical = 23168 ; free virtual = 49310 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.383 ; gain = 497.531 ; free physical = 23218 ; free virtual = 49360 Phase 2 Final Placement Cleanup INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 23218 ; free virtual = 49360 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 23218 ; free virtual = 49360 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.383 ; gain = 497.531 ; free physical = 24023 ; free virtual = 50165 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Ending Placer Task | Checksum: 110ed1b10 Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 4 #of bits: 30 #of tags: 3 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/cfg_int' GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_005 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.383 ; gain = 497.531 ; free physical = 24026 ; free virtual = 50168 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.383 ; gain = 575.562 ; free physical = 24013 ; free virtual = 50155 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 24017 ; free virtual = 50160 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 24017 ; free virtual = 50160 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 24017 ; free virtual = 50159 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Running DRC as a precondition to command route_design --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 24015 ; free virtual = 50157 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 24015 ; free virtual = 50157 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 24014 ; free virtual = 50156 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 24014 ; free virtual = 50156 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 24023 ; free virtual = 50165 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 24061 ; free virtual = 50203 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 24049 ; free virtual = 50191 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 23898 ; free virtual = 50040 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 23614 ; free virtual = 49756 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 23589 ; free virtual = 49732 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 23537 ; free virtual = 49680 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 23536 ; free virtual = 49679 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 23484 ; free virtual = 49627 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 23441 ; free virtual = 49584 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:22 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 23438 ; free virtual = 49581 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 23399 ; free virtual = 49542 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 23368 ; free virtual = 49511 INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:55] Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:755] --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:867] --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1819] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 --------------------------------------------------------------------------------- Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Start Final Netlist Cleanup --------------------------------------------------------------------------------- Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 23388 ; free virtual = 49531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 23387 ; free virtual = 49531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 23387 ; free virtual = 49530 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 23361 ; free virtual = 49504 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 23361 ; free virtual = 49504 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Placer Task Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 23356 ; free virtual = 49499 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.715 ; gain = 0.000 ; free physical = 23347 ; free virtual = 49490 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1470.715 ; gain = 0.000 ; free physical = 23338 ; free virtual = 49481 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 23338 ; free virtual = 49481 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 23335 ; free virtual = 49478 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 23332 ; free virtual = 49476 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 23332 ; free virtual = 49475 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 23331 ; free virtual = 49474 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 23327 ; free virtual = 49470 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 23327 ; free virtual = 49470 INFO: [Project 1-571] Translating synthesized netlist ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Creating bitstream... INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14793 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1813.207 ; gain = 0.000 ; free physical = 22667 ; free virtual = 48810 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 22613 ; free virtual = 48756 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 22608 ; free virtual = 48751 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 22607 ; free virtual = 48750 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 22607 ; free virtual = 48750 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 22604 ; free virtual = 48748 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 435.531 ; free physical = 22599 ; free virtual = 48742 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1901.250 ; gain = 499.562 ; free physical = 22597 ; free virtual = 48741 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1814.445 ; gain = 0.000 ; free physical = 22648 ; free virtual = 48796 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 22627 ; free virtual = 48774 Phase 1.3 Build Placer Netlist Model Starting Routing Task Phase 1.3 Build Placer Netlist Model | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 22620 ; free virtual = 48767 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 22620 ; free virtual = 48767 Phase 1 Placer Initialization | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 22619 ; free virtual = 48767 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1bef48727 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 22619 ; free virtual = 48767 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: df085f83 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1902.488 ; gain = 436.531 ; free physical = 22620 ; free virtual = 48768 23 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1902.488 ; gain = 500.562 ; free physical = 22620 ; free virtual = 48768 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2b0ad97a ConstDB: 0 ShapeSum: b3fd8609 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 22262 ; free virtual = 48409 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 22283 ; free virtual = 48430 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22261 ; free virtual = 48409 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 22166 ; free virtual = 48313 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 22160 ; free virtual = 48308 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22131 ; free virtual = 48279 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22095 ; free virtual = 48242 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22089 ; free virtual = 48237 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22081 ; free virtual = 48229 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22079 ; free virtual = 48226 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22075 ; free virtual = 48222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22072 ; free virtual = 48219 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22069 ; free virtual = 48216 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22061 ; free virtual = 48208 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 22060 ; free virtual = 48207 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:53:25 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:24 . Memory (MB): peak = 2532.227 ; gain = 339.105 ; free physical = 21956 ; free virtual = 48103 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:53:25 2019... INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 21998 ; free virtual = 48145 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22001 ; free virtual = 48148 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22006 ; free virtual = 48153 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22009 ; free virtual = 48156 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22011 ; free virtual = 48158 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22012 ; free virtual = 48159 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22016 ; free virtual = 48163 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22029 ; free virtual = 48176 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 22035 ; free virtual = 48182 INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 22852 ; free virtual = 48999 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_002/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_006 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 520.531 ; free physical = 22906 ; free virtual = 49054 Phase 1.3 Build Placer Netlist Model INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 520.531 ; free physical = 22875 ; free virtual = 49023 Phase 1.4 Constrain Clocks/Macros INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 520.531 ; free physical = 22859 ; free virtual = 49006 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 520.531 ; free physical = 22844 ; free virtual = 48991 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 520.531 ; free physical = 22838 ; free virtual = 48985 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 520.531 ; free physical = 22832 ; free virtual = 48979 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 22831 ; free virtual = 48978 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 22694 ; free virtual = 48841 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Project 1-570] Preparing netlist for logic optimization Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.211 ; gain = 0.000 ; free physical = 22571 ; free virtual = 48718 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 22513 ; free virtual = 48661 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1547.953 ; gain = 0.000 ; free physical = 22459 ; free virtual = 48606 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 22453 ; free virtual = 48600 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 22437 ; free virtual = 48584 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 22435 ; free virtual = 48582 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 22437 ; free virtual = 48584 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 22437 ; free virtual = 48584 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 22437 ; free virtual = 48584 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.254 ; gain = 534.562 ; free physical = 22436 ; free virtual = 48584 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.58 . Memory (MB): peak = 1547.953 ; gain = 0.000 ; free physical = 22409 ; free virtual = 48557 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:923] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 22266 ; free virtual = 48414 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Starting Routing Task --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 22247 ; free virtual = 48395 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 22247 ; free virtual = 48395 --------------------------------------------------------------------------------- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 22170 ; free virtual = 48318 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15054 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 22215 ; free virtual = 48363 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 22215 ; free virtual = 48362 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Starting Placer Task Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 22124 ; free virtual = 48272 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1296e3a58 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 22122 ; free virtual = 48270 Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1481.742 ; gain = 0.000 ; free physical = 22122 ; free virtual = 48269 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1481.742 ; gain = 0.000 ; free physical = 22120 ; free virtual = 48268 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.203 ; gain = 0.000 ; free physical = 21566 ; free virtual = 47714 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 21547 ; free virtual = 47695 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 21540 ; free virtual = 47688 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 21536 ; free virtual = 47684 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 21533 ; free virtual = 47681 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 21528 ; free virtual = 47676 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1987.246 ; gain = 516.531 ; free physical = 21525 ; free virtual = 47673 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.246 ; gain = 581.562 ; free physical = 21525 ; free virtual = 47672 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 21332 ; free virtual = 47480 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 21262 ; free virtual = 47410 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 21312 ; free virtual = 47460 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 21258 ; free virtual = 47405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 21245 ; free virtual = 47392 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 21245 ; free virtual = 47392 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 21242 ; free virtual = 47389 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 21242 ; free virtual = 47389 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 21241 ; free virtual = 47389 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 21241 ; free virtual = 47389 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 21241 ; free virtual = 47388 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 21241 ; free virtual = 47389 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 21243 ; free virtual = 47391 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:475] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 21191 ; free virtual = 47340 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 21188 ; free virtual = 47337 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 21188 ; free virtual = 47337 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 21168 ; free virtual = 47316 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 20821 ; free virtual = 46969 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 20516 ; free virtual = 46664 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e39310c0 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 20503 ; free virtual = 46651 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15230 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 20414 ; free virtual = 46562 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 20106 ; free virtual = 46254 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 19976 ; free virtual = 46124 Phase 1.3 Build Placer Netlist Model Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 19917 ; free virtual = 46066 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19841 ; free virtual = 45989 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 19717 ; free virtual = 45866 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 19718 ; free virtual = 45866 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19707 ; free virtual = 45856 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19706 ; free virtual = 45854 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19705 ; free virtual = 45853 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19704 ; free virtual = 45853 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 19704 ; free virtual = 45853 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19704 ; free virtual = 45853 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19704 ; free virtual = 45852 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19704 ; free virtual = 45852 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 19704 ; free virtual = 45853 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 19706 ; free virtual = 45855 Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 19706 ; free virtual = 45855 Phase 1.4 Constrain Clocks/Macros INFO: [Project 1-571] Translating synthesized netlist Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 19693 ; free virtual = 45841 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 19694 ; free virtual = 45842 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 19692 ; free virtual = 45840 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 19694 ; free virtual = 45842 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 19693 ; free virtual = 45842 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1e1594fd1 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 19683 ; free virtual = 45832 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 278abb5b7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 19681 ; free virtual = 45829 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 278abb5b7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 19680 ; free virtual = 45828 Phase 1 Placer Initialization | Checksum: 278abb5b7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 19683 ; free virtual = 45831 Phase 2 Global Placement Phase 1 Build RT Design | Checksum: 107963fbc Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2135.066 ; gain = 50.668 ; free physical = 19662 ; free virtual = 45810 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 107963fbc Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2144.055 ; gain = 59.656 ; free physical = 19616 ; free virtual = 45765 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 107963fbc Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2144.055 ; gain = 59.656 ; free physical = 19616 ; free virtual = 45765 INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-570] Preparing netlist for logic optimization Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1c2f462cb Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.484 ; gain = 95.086 ; free physical = 19567 ; free virtual = 45715 Phase 3 Initial Routing Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 19565 ; free virtual = 45713 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 19585 ; free virtual = 45734 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.484 ; gain = 95.086 ; free physical = 19583 ; free virtual = 45731 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 4.1 Global Iteration 0 | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.484 ; gain = 95.086 ; free physical = 19580 ; free virtual = 45729 Phase 4 Rip-up And Reroute | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.484 ; gain = 95.086 ; free physical = 19579 ; free virtual = 45728 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.484 ; gain = 95.086 ; free physical = 19578 ; free virtual = 45727 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 19577 ; free virtual = 45726 Phase 2 Global Placement Phase 6.1 Hold Fix Iter | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.484 ; gain = 95.086 ; free physical = 19577 ; free virtual = 45725 Phase 6 Post Hold Fix | Checksum: 1c2f462cb Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.484 ; gain = 95.086 ; free physical = 19575 ; free virtual = 45724 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.484 ; gain = 95.086 ; free physical = 19586 ; free virtual = 45734 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.484 ; gain = 95.086 ; free physical = 19577 ; free virtual = 45725 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1c2f462cb Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2179.484 ; gain = 95.086 ; free physical = 19564 ; free virtual = 45712 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2179.484 ; gain = 95.086 ; free physical = 19606 ; free virtual = 45754 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:45 . Memory (MB): peak = 2218.273 ; gain = 165.891 ; free physical = 19606 ; free virtual = 45754 Writing placer database... Phase 2 Global Placement | Checksum: 27094be7a Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19581 ; free virtual = 45732 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 27094be7a Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19571 ; free virtual = 45723 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 215570181 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19569 ; free virtual = 45721 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1ef31df4c Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19560 ; free virtual = 45714 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1b8e63fb1 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19559 ; free virtual = 45713 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19500 ; free virtual = 45656 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19499 ; free virtual = 45656 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 18eec566c Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19497 ; free virtual = 45654 Phase 3 Detail Placement | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19496 ; free virtual = 45653 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19490 ; free virtual = 45648 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19490 ; free virtual = 45647 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19489 ; free virtual = 45647 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19487 ; free virtual = 45645 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18eec566c Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19486 ; free virtual = 45644 Ending Placer Task | Checksum: 146bf3d33 Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 19498 ; free virtual = 45657 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 19498 ; free virtual = 45656 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 19472 ; free virtual = 45633 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 19485 ; free virtual = 45650 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19483 ; free virtual = 45650 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19470 ; free virtual = 45638 Phase 3.2 Commit Most Macros & LUTRAMs WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 621f9429 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19433 ; free virtual = 45605 Phase 3.3 Area Swap Optimization Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2218.273 ; gain = 0.000 ; free physical = 19408 ; free virtual = 45585 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19414 ; free virtual = 45591 Phase 3.4 Pipeline Register Optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:251] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Starting Placer Task INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 19419 ; free virtual = 45596 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:16] Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1a69706bf Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 19417 ; free virtual = 45595 Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19411 ; free virtual = 45589 Phase 3.5 Small Shape Detail Placement WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 19450 ; free virtual = 45629 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 19456 ; free virtual = 45636 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 19455 ; free virtual = 45635 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.961 ; gain = 115.508 ; free physical = 19450 ; free virtual = 45602 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:38 . Memory (MB): peak = 2054.172 ; gain = 119.668 ; free physical = 19372 ; free virtual = 45524 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:38 . Memory (MB): peak = 2060.160 ; gain = 125.656 ; free physical = 19341 ; free virtual = 45493 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 831abe83 Time (s): cpu = 00:00:39 ; elapsed = 00:00:38 . Memory (MB): peak = 2060.160 ; gain = 125.656 ; free physical = 19342 ; free virtual = 45494 Phase 1 Build RT Design | Checksum: 9c37998b Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2053.934 ; gain = 120.668 ; free physical = 19336 ; free virtual = 45488 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:39 ; elapsed = 00:00:38 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19318 ; free virtual = 45470 Phase 3 Initial Routing Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 9c37998b Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2058.922 ; gain = 125.656 ; free physical = 19299 ; free virtual = 45451 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 9c37998b Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2058.922 ; gain = 125.656 ; free physical = 19299 ; free virtual = 45451 Running DRC as a precondition to command write_bitstream Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19275 ; free virtual = 45426 Phase 3.6 Re-assign LUT pins Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19240 ; free virtual = 45392 Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19236 ; free virtual = 45388 Phase 3.7 Pipeline Register Optimization Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19233 ; free virtual = 45384 Phase 4 Rip-up And Reroute | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19232 ; free virtual = 45384 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19231 ; free virtual = 45383 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19233 ; free virtual = 45385 Phase 6 Post Hold Fix | Checksum: 3fd9fb11 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2066.215 ; gain = 131.711 ; free physical = 19235 ; free virtual = 45387 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 12be4f0f0 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 19233 ; free virtual = 45385 Phase 3 Initial Routing Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2067.215 ; gain = 132.711 ; free physical = 19225 ; free virtual = 45377 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2069.215 ; gain = 134.711 ; free physical = 19222 ; free virtual = 45374 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 3fd9fb11 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2069.215 ; gain = 134.711 ; free physical = 19221 ; free virtual = 45373 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2069.215 ; gain = 134.711 ; free physical = 19247 ; free virtual = 45399 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2108.004 ; gain = 205.516 ; free physical = 19246 ; free virtual = 45398 Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19231 ; free virtual = 45382 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 19230 ; free virtual = 45382 Writing placer database... Writing XDEF routing. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 19228 ; free virtual = 45381 Phase 4 Rip-up And Reroute | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 19228 ; free virtual = 45380 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 19228 ; free virtual = 45380 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 19228 ; free virtual = 45380 Phase 6 Post Hold Fix | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 19228 ; free virtual = 45380 Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2108.004 ; gain = 0.000 ; free physical = 19226 ; free virtual = 45379 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 7 Route finalize | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2065.977 ; gain = 132.711 ; free physical = 19190 ; free virtual = 45342 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.977 ; gain = 134.711 ; free physical = 19187 ; free virtual = 45339 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 12be4f0f0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.977 ; gain = 134.711 ; free physical = 19187 ; free virtual = 45339 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.977 ; gain = 134.711 ; free physical = 19220 ; free virtual = 45372 Routing Is Done. 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2106.766 ; gain = 205.516 ; free physical = 19219 ; free virtual = 45371 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19220 ; free virtual = 45372 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2106.766 ; gain = 0.000 ; free physical = 19193 ; free virtual = 45347 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19177 ; free virtual = 45329 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19133 ; free virtual = 45285 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19138 ; free virtual = 45290 Phase 4.4 Final Placement Cleanup Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 INFO: [DRC 23-27] Running DRC with 8 threads Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19200 ; free virtual = 45352 Running DRC as a precondition to command write_bitstream Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19211 ; free virtual = 45363 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 19195 ; free virtual = 45348 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 19196 ; free virtual = 45348 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 18518 ; free virtual = 44671 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading data files... Loading data files... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 190af02d6 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 18440 ; free virtual = 44597 Phase 1.3 Build Placer Netlist Model Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 2280168bc Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 18443 ; free virtual = 44596 Phase 1.4 Constrain Clocks/Macros Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2066.176 ; gain = 42.668 ; free physical = 18442 ; free virtual = 44595 Phase 1.4 Constrain Clocks/Macros | Checksum: 2280168bc Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 18442 ; free virtual = 44595 Phase 1 Placer Initialization | Checksum: 2280168bc Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 18441 ; free virtual = 44593 Phase 2 Global Placement Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 18407 ; free virtual = 44559 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 18407 ; free virtual = 44559 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 18372 ; free virtual = 44524 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 18362 ; free virtual = 44515 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2083.469 ; gain = 59.961 ; free physical = 18360 ; free virtual = 44513 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18338 ; free virtual = 44491 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 18261 ; free virtual = 44413 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 18269 ; free virtual = 44422 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 18268 ; free virtual = 44420 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 18267 ; free virtual = 44420 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 18266 ; free virtual = 44418 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 18266 ; free virtual = 44418 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 18302 ; free virtual = 44455 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2087.469 ; gain = 63.961 ; free physical = 18299 ; free virtual = 44452 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 18276 ; free virtual = 44428 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 18314 ; free virtual = 44466 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2127.258 ; gain = 135.766 ; free physical = 18312 ; free virtual = 44464 Writing placer database... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18198 ; free virtual = 44351 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18195 ; free virtual = 44348 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18200 ; free virtual = 44353 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18207 ; free virtual = 44361 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18216 ; free virtual = 44370 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18216 ; free virtual = 44370 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18216 ; free virtual = 44370 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18217 ; free virtual = 44371 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.949 ; gain = 246.488 ; free physical = 18220 ; free virtual = 44373 Writing XDEF routing. INFO: [Project 1-571] Translating synthesized netlist Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2127.258 ; gain = 0.000 ; free physical = 18205 ; free virtual = 44360 Phase 1 Build RT Design | Checksum: 1016daa37 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2057.938 ; gain = 93.668 ; free physical = 18186 ; free virtual = 44343 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1016daa37 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2063.926 ; gain = 99.656 ; free physical = 18144 ; free virtual = 44298 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1016daa37 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2063.926 ; gain = 99.656 ; free physical = 18144 ; free virtual = 44297 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: aef8114b Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.980 ; gain = 105.711 ; free physical = 18074 ; free virtual = 44226 Phase 3 Initial Routing INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: aef8114b Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 18048 ; free virtual = 44201 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: aef8114b Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 18048 ; free virtual = 44201 Phase 4 Rip-up And Reroute | Checksum: aef8114b Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 18047 ; free virtual = 44200 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: aef8114b Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 18047 ; free virtual = 44200 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: aef8114b Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 18047 ; free virtual = 44200 Phase 6 Post Hold Fix | Checksum: aef8114b Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 18047 ; free virtual = 44200 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: aef8114b Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2070.980 ; gain = 106.711 ; free physical = 18066 ; free virtual = 44219 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: aef8114b Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.980 ; gain = 109.711 ; free physical = 18068 ; free virtual = 44221 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: aef8114b Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.980 ; gain = 109.711 ; free physical = 18065 ; free virtual = 44218 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.980 ; gain = 109.711 ; free physical = 18100 ; free virtual = 44253 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2112.770 ; gain = 180.516 ; free physical = 18100 ; free virtual = 44253 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading data files... Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2112.770 ; gain = 0.000 ; free physical = 18092 ; free virtual = 44247 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Global Placement | Checksum: 21fea717f Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18093 ; free virtual = 44247 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 21fea717f Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18090 ; free virtual = 44243 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b3a364ee Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18082 ; free virtual = 44236 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 18d7e42b9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18064 ; free virtual = 44217 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 15732a31e Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 18059 ; free virtual = 44212 Phase 3.5 Small Shape Detail Placement INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3.5 Small Shape Detail Placement | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17962 ; free virtual = 44116 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17975 ; free virtual = 44129 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17987 ; free virtual = 44140 Phase 3 Detail Placement | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17991 ; free virtual = 44144 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17970 ; free virtual = 44123 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17954 ; free virtual = 44107 Phase 4.3 Placer Reporting Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.3 Placer Reporting | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17951 ; free virtual = 44104 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17943 ; free virtual = 44096 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1c9e3899d Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17941 ; free virtual = 44094 Ending Placer Task | Checksum: 181b67064 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17952 ; free virtual = 44106 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 17952 ; free virtual = 44106 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9d16c75a ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading data files... INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1424.941 ; gain = 342.047 ; free physical = 17534 ; free virtual = 43687 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 17210 ; free virtual = 43364 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1585d46d4 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 17198 ; free virtual = 43351 Loading site data... Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Loading route data... Processing options... Creating bitmap... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 16795 ; free virtual = 42949 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2063.930 ; gain = 44.668 ; free physical = 16768 ; free virtual = 42921 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.918 ; gain = 49.656 ; free physical = 16728 ; free virtual = 42881 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.918 ; gain = 49.656 ; free physical = 16727 ; free virtual = 42881 Creating bitstream... Creating bitstream... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 151febe35 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 16711 ; free virtual = 42864 Phase 1.3 Build Placer Netlist Model Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2078.973 ; gain = 59.711 ; free physical = 16700 ; free virtual = 42853 Phase 3 Initial Routing Phase 1.3 Build Placer Netlist Model | Checksum: 1e951241b Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 16697 ; free virtual = 42851 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1e951241b Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 16695 ; free virtual = 42849 Phase 1 Placer Initialization | Checksum: 1e951241b Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 16693 ; free virtual = 42847 Phase 2 Global Placement Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16659 ; free virtual = 42813 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16647 ; free virtual = 42801 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16647 ; free virtual = 42800 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16646 ; free virtual = 42800 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16646 ; free virtual = 42799 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16646 ; free virtual = 42799 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2080.973 ; gain = 61.711 ; free physical = 16643 ; free virtual = 42797 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.973 ; gain = 63.711 ; free physical = 16644 ; free virtual = 42797 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.973 ; gain = 63.711 ; free physical = 16641 ; free virtual = 42795 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.973 ; gain = 63.711 ; free physical = 16676 ; free virtual = 42829 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2121.762 ; gain = 134.516 ; free physical = 16675 ; free virtual = 42828 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2121.762 ; gain = 0.000 ; free physical = 16635 ; free virtual = 42790 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Loading site data... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... Writing bitstream ./design.bit... Phase 2 Global Placement | Checksum: 1e13a2cde Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 16418 ; free virtual = 42579 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1e13a2cde Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 16453 ; free virtual = 42614 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 262698c70 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 16516 ; free virtual = 42677 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23c446a3b Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 16843 ; free virtual = 43004 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 205f8caa0 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 16930 ; free virtual = 43092 Phase 3.5 Small Shape Detail Placement INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 3.5 Small Shape Detail Placement | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17022 ; free virtual = 43184 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17025 ; free virtual = 43187 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17020 ; free virtual = 43182 Phase 3 Detail Placement | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 16996 ; free virtual = 43158 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 16988 ; free virtual = 43150 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 16977 ; free virtual = 43139 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 16989 ; free virtual = 43151 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 16998 ; free virtual = 43160 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1eba3aebc Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 16993 ; free virtual = 43155 Ending Placer Task | Checksum: 1a3769583 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 17028 ; free virtual = 43190 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 17017 ; free virtual = 43179 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: bed6ec79 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:54:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 2449.871 ; gain = 343.105 ; free physical = 16842 ; free virtual = 43004 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:54:28 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:54:29 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Loading data files... 40 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:27 . Memory (MB): peak = 2450.109 ; gain = 342.105 ; free physical = 17511 ; free virtual = 43673 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:54:29 2019... Loading site data... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_004 Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 4 #of bits: 39 #of tags: 2 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 2 max #of candidates: 2 avg #of candidates: 2.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/monitor_int' GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Creating bitstream... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. Writing bitstream ./design.bit... INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.957 ; gain = 41.668 ; free physical = 19029 ; free virtual = 45185 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 19037 ; free virtual = 45193 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 143717b54 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 19035 ; free virtual = 45192 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1aab43f05 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2087.375 ; gain = 61.086 ; free physical = 18930 ; free virtual = 45086 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1aab43f05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18878 ; free virtual = 45035 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1aab43f05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18875 ; free virtual = 45031 Phase 4 Rip-up And Reroute | Checksum: 1aab43f05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18874 ; free virtual = 45031 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1aab43f05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18873 ; free virtual = 45030 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1aab43f05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18869 ; free virtual = 45026 Phase 6 Post Hold Fix | Checksum: 1aab43f05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18867 ; free virtual = 45024 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1aab43f05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 18858 ; free virtual = 45015 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1aab43f05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2090.375 ; gain = 64.086 ; free physical = 18857 ; free virtual = 45014 Phase 9 Depositing Routes INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 9 Depositing Routes | Checksum: 1aab43f05 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 18857 ; free virtual = 45014 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.461 ; gain = 0.000 ; free physical = 18858 ; free virtual = 45015 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 18896 ; free virtual = 45053 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2130.164 ; gain = 135.891 ; free physical = 18896 ; free virtual = 45053 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading site data... Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:54:40 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2471.363 ; gain = 344.105 ; free physical = 18893 ; free virtual = 45050 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:54:40 2019... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:54:40 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Loading route data... 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2454.875 ; gain = 342.105 ; free physical = 18922 ; free virtual = 45108 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:54:40 2019... Processing options... Write XDEF Complete: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.39 . Memory (MB): peak = 2130.164 ; gain = 0.000 ; free physical = 18932 ; free virtual = 45119 Creating bitmap... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1d38ee6f1 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 19946 ; free virtual = 46134 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Phase 1.3 Build Placer Netlist Model | Checksum: 26ae14cd7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 20665 ; free virtual = 46850 Phase 1.4 Constrain Clocks/Macros Config size: 1060815 words Number of configuration frames: 9996 Phase 1.4 Constrain Clocks/Macros | Checksum: 26ae14cd7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 20796 ; free virtual = 46980 DONE Phase 1 Placer Initialization | Checksum: 26ae14cd7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 20803 ; free virtual = 46987 Phase 2 Global Placement Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_005 touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_002/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:54:41 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:41 . Memory (MB): peak = 2607.434 ; gain = 389.160 ; free physical = 20671 ; free virtual = 46855 Running DRC as a precondition to command write_bitstream INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:54:41 2019... Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer touch build/specimen_002/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_003 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 1a640bfe0 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 21508 ; free virtual = 47694 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1a640bfe0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 21463 ; free virtual = 47648 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1a640bfe0 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 21546 ; free virtual = 47732 Phase 2 Global Placement | Checksum: 262ca559a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21475 ; free virtual = 47660 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 262ca559a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21470 ; free virtual = 47655 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 23e660b1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21470 ; free virtual = 47656 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21840e8ea Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21479 ; free virtual = 47666 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1e1f5494f Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21477 ; free virtual = 47666 Phase 3.5 Small Shape Detail Placement Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 17f6b07bf Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 21605 ; free virtual = 47796 Phase 3 Initial Routing Phase 3.5 Small Shape Detail Placement | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21577 ; free virtual = 47768 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21576 ; free virtual = 47767 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21439a1bf Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21577 ; free virtual = 47768 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 63a0e4fc Phase 3 Detail Placement | Checksum: 21439a1bf Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 21579 ; free virtual = 47770 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21579 ; free virtual = 47770 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Post Commit Optimization | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21573 ; free virtual = 47763 Phase 4.1 Global Iteration 0 | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 21572 ; free virtual = 47763 Phase 4 Rip-up And Reroute | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 21572 ; free virtual = 47763 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 21571 ; free virtual = 47762 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 4.2 Post Placement Cleanup Phase 6.1 Hold Fix Iter | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 21570 ; free virtual = 47761 Phase 6 Post Hold Fix | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 21568 ; free virtual = 47759 Phase 4.2 Post Placement Cleanup | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21564 ; free virtual = 47755 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21557 ; free virtual = 47748 Phase 4.4 Final Placement Cleanup Phase 7 Route finalize Phase 4.4 Final Placement Cleanup | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21544 ; free virtual = 47735 Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21439a1bf Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21531 ; free virtual = 47722 Ending Placer Task | Checksum: 1cc0c8886 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 21527 ; free virtual = 47717 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.547 ; gain = 659.605 ; free physical = 21526 ; free virtual = 47717 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 21543 ; free virtual = 47734 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 63a0e4fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 21542 ; free virtual = 47732 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 63a0e4fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 21558 ; free virtual = 47749 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 21594 ; free virtual = 47784 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2140.020 ; gain = 47.473 ; free physical = 21595 ; free virtual = 47786 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2140.020 ; gain = 0.000 ; free physical = 21564 ; free virtual = 47757 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e76cdf7c ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2130.430 ; gain = 31.227 ; free physical = 21568 ; free virtual = 47764 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2137.418 ; gain = 38.215 ; free physical = 21529 ; free virtual = 47724 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2137.418 ; gain = 38.215 ; free physical = 21528 ; free virtual = 47724 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 21470 ; free virtual = 47666 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 21441 ; free virtual = 47636 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 21449 ; free virtual = 47645 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 21449 ; free virtual = 47645 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 21449 ; free virtual = 47645 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 21449 ; free virtual = 47645 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 21449 ; free virtual = 47645 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Loading data files... Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 21439 ; free virtual = 47635 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 21438 ; free virtual = 47633 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 21438 ; free virtual = 47633 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2156.473 ; gain = 57.270 ; free physical = 21473 ; free virtual = 47668 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2195.262 ; gain = 96.059 ; free physical = 21474 ; free virtual = 47669 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing placer database... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:54:53 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2460.867 ; gain = 339.105 ; free physical = 21306 ; free virtual = 47512 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:54:53 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_004 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19525 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19532 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2195.262 ; gain = 0.000 ; free physical = 21908 ; free virtual = 48090 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 137afd744 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 21416 ; free virtual = 47583 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 137afd744 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 21378 ; free virtual = 47546 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 137afd744 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 21378 ; free virtual = 47545 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 11278bc6b Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 9.684 ; free physical = 21313 ; free virtual = 47481 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 9.684 ; free physical = 21264 ; free virtual = 47432 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 9.684 ; free physical = 21293 ; free virtual = 47460 Phase 4 Rip-up And Reroute | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 9.684 ; free physical = 21293 ; free virtual = 47460 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 9.684 ; free physical = 21293 ; free virtual = 47460 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 9.684 ; free physical = 21293 ; free virtual = 47460 Phase 6 Post Hold Fix | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2102.230 ; gain = 9.684 ; free physical = 21292 ; free virtual = 47460 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.230 ; gain = 9.684 ; free physical = 21287 ; free virtual = 47454 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: ceaeb1c8 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.230 ; gain = 9.684 ; free physical = 21285 ; free virtual = 47453 Phase 9 Depositing Routes Loading site data... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } Phase 9 Depositing Routes | Checksum: ceaeb1c8 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.230 ; gain = 9.684 ; free physical = 21276 ; free virtual = 47444 ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2102.230 ; gain = 9.684 ; free physical = 21311 ; free virtual = 47479 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2141.020 ; gain = 48.473 ; free physical = 21309 ; free virtual = 47477 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2141.020 ; gain = 0.000 ; free physical = 21234 ; free virtual = 47405 Loading route data... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Processing options... Creating bitmap... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading data files... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19708 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 21094 ; free virtual = 47262 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19744 Creating bitstream... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 20938 ; free virtual = 47106 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 20745 ; free virtual = 46913 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:168] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Writing bitstream ./design.bit... INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/top.v:2] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 20650 ; free virtual = 46823 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 20647 ; free virtual = 46819 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 20762 ; free virtual = 46935 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 21014 ; free virtual = 47187 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 21012 ; free virtual = 47186 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 21013 ; free virtual = 47186 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 20991 ; free virtual = 47165 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19803 Phase 1 Build RT Design | Checksum: 12358ba72 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 20775 ; free virtual = 46949 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 12358ba72 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 20735 ; free virtual = 46908 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 12358ba72 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 20734 ; free virtual = 46908 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: eb842b41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20702 ; free virtual = 46875 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20666 ; free virtual = 46839 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20655 ; free virtual = 46828 Phase 4 Rip-up And Reroute | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20656 ; free virtual = 46829 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20655 ; free virtual = 46828 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20655 ; free virtual = 46828 Phase 6 Post Hold Fix | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20655 ; free virtual = 46828 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Writing bitstream ./design.bit... Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20651 ; free virtual = 46825 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20650 ; free virtual = 46824 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f7bb427e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20648 ; free virtual = 46824 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20684 ; free virtual = 46859 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2140.020 ; gain = 47.473 ; free physical = 20684 ; free virtual = 46860 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2140.020 ; gain = 0.000 ; free physical = 20774 ; free virtual = 46954 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:55:11 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:39 ; elapsed = 00:00:31 . Memory (MB): peak = 2470.270 ; gain = 340.105 ; free physical = 20893 ; free virtual = 47071 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:55:11 2019... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 Loading site data... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 21695 ; free virtual = 47874 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 21584 ; free virtual = 47764 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:55:14 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2475.125 ; gain = 335.105 ; free physical = 21469 ; free virtual = 47653 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:55:14 2019... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 22488 ; free virtual = 48678 --------------------------------------------------------------------------------- Config size: 1060815 words Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Number of configuration frames: 9996 --------------------------------------------------------------------------------- DONE Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 22488 ; free virtual = 48673 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:64] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:610] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:631] Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 22440 ; free virtual = 48625 WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:638] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:659] --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:659] Loading part: xc7z020clg400-1 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 22444 ; free virtual = 48629 --------------------------------------------------------------------------------- Creating bitstream... INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/top.v:2] INFO: [Device 21-403] Loading part xc7z020clg400-1 touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_007 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 22440 ; free virtual = 48625 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 22443 ; free virtual = 48628 --------------------------------------------------------------------------------- Command: synth_design -top top --------------------------------------------------------------------------------- Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 22459 ; free virtual = 48645 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 22423 ; free virtual = 48609 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 22392 ; free virtual = 48578 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 22362 ; free virtual = 48549 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 22362 ; free virtual = 48549 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 22348 ; free virtual = 48534 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 22340 ; free virtual = 48526 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 22281 ; free virtual = 48467 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 22217 ; free virtual = 48403 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 22213 ; free virtual = 48399 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 22193 ; free virtual = 48379 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 22190 ; free virtual = 48376 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 22187 ; free virtual = 48372 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 22184 ; free virtual = 48370 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 22180 ; free virtual = 48366 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 22176 ; free virtual = 48362 Loading data files... Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.688 ; gain = 225.230 ; free physical = 22177 ; free virtual = 48363 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 22163 ; free virtual = 48349 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 22159 ; free virtual = 48344 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 22155 ; free virtual = 48340 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 22153 ; free virtual = 48339 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 22154 ; free virtual = 48339 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 22153 ; free virtual = 48339 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 22153 ; free virtual = 48338 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 22150 ; free virtual = 48335 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 22150 ; free virtual = 48336 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 19991 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 22049 ; free virtual = 48235 --------------------------------------------------------------------------------- Loading site data... Loading route data... Writing bitstream ./design.bit... Processing options... Creating bitmap... INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:55:22 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 2533.367 ; gain = 338.105 ; free physical = 21828 ; free virtual = 48017 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:55:22 2019... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_003/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_004 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:30 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 22823 ; free virtual = 49013 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 22822 ; free virtual = 49011 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 22811 ; free virtual = 49000 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 22797 ; free virtual = 48988 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 22810 ; free virtual = 48999 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 22784 ; free virtual = 48974 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 22773 ; free virtual = 48963 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22770 ; free virtual = 48960 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 22804 ; free virtual = 48994 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 22803 ; free virtual = 48994 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 22802 ; free virtual = 48993 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 22802 ; free virtual = 48993 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 22802 ; free virtual = 48993 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 22801 ; free virtual = 48992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 22801 ; free virtual = 48991 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Starting Placer Task Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 22799 ; free virtual = 48990 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 22802 ; free virtual = 48993 INFO: [Project 1-571] Translating synthesized netlist INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1469.711 ; gain = 0.000 ; free physical = 22786 ; free virtual = 48977 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1469.711 ; gain = 0.000 ; free physical = 22786 ; free virtual = 48977 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 22743 ; free virtual = 48934 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 22729 ; free virtual = 48920 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22755 ; free virtual = 48946 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22752 ; free virtual = 48943 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22713 ; free virtual = 48904 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22710 ; free virtual = 48901 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22707 ; free virtual = 48898 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22705 ; free virtual = 48896 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22700 ; free virtual = 48890 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22688 ; free virtual = 48879 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 22687 ; free virtual = 48877 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization Loading site data... INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading route data... --------------------------------------------------------------------------------- Processing options... Creating bitmap... Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 22587 ; free virtual = 48778 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: 15ca2bf97 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2084.547 ; gain = 0.000 ; free physical = 22786 ; free virtual = 48981 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15ca2bf97 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2084.547 ; gain = 0.000 ; free physical = 22774 ; free virtual = 48969 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15ca2bf97 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2084.547 ; gain = 0.000 ; free physical = 22774 ; free virtual = 48969 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: fe41f556 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 22680 ; free virtual = 48875 Phase 3 Initial Routing INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2] Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 22657 ; free virtual = 48852 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 22671 ; free virtual = 48865 Phase 4 Rip-up And Reroute | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 22670 ; free virtual = 48865 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 22669 ; free virtual = 48864 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 22669 ; free virtual = 48864 Phase 6 Post Hold Fix | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 22668 ; free virtual = 48863 INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:888] Phase 7 Route finalize WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 22658 ; free virtual = 48853 Phase 8 Verifying routed nets Verification completed successfully INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 8 Verifying routed nets | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 22656 ; free virtual = 48851 Phase 9 Depositing Routes INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 9 Depositing Routes | Checksum: e279f4d5 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 22669 ; free virtual = 48864 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2102.234 ; gain = 17.688 ; free physical = 22713 ; free virtual = 48908 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2141.023 ; gain = 56.477 ; free physical = 22718 ; free virtual = 48913 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1397.691 ; gain = 314.797 ; free physical = 22717 ; free virtual = 48912 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Writing placer database... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.30 . Memory (MB): peak = 2141.023 ; gain = 0.000 ; free physical = 22672 ; free virtual = 48869 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.723 ; gain = 0.000 ; free physical = 22521 ; free virtual = 48716 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1463.723 ; gain = 0.000 ; free physical = 22520 ; free virtual = 48716 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/top.v:2] INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:55:31 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:29 . Memory (MB): peak = 2474.125 ; gain = 333.105 ; free physical = 22470 ; free virtual = 48666 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:55:31 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 22629 ; free virtual = 48824 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_008 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 23521 ; free virtual = 49719 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 23495 ; free virtual = 49692 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 23491 ; free virtual = 49689 Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 23366 ; free virtual = 49564 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 23364 ; free virtual = 49562 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20311 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20353 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 1338.074 ; gain = 242.152 ; free physical = 23250 ; free virtual = 49452 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:55:39 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2473.125 ; gain = 333.105 ; free physical = 23187 ; free virtual = 49389 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:55:39 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_009 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:32 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 23931 ; free virtual = 50147 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 1342.105 ; gain = 246.184 ; free physical = 23730 ; free virtual = 49953 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 23561 ; free virtual = 49765 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.199 ; gain = 0.000 ; free physical = 23531 ; free virtual = 49736 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.242 ; gain = 516.531 ; free physical = 23510 ; free virtual = 49730 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.242 ; gain = 516.531 ; free physical = 23492 ; free virtual = 49716 Phase 1.4 Constrain Clocks/Macros INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.242 ; gain = 516.531 ; free physical = 23493 ; free virtual = 49717 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.242 ; gain = 516.531 ; free physical = 23490 ; free virtual = 49714 Phase 2 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 23490 ; free virtual = 49714 Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.242 ; gain = 516.531 ; free physical = 23488 ; free virtual = 49712 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.242 ; gain = 516.531 ; free physical = 23484 ; free virtual = 49708 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.242 ; gain = 580.562 ; free physical = 23483 ; free virtual = 49707 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 23381 ; free virtual = 49605 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 23403 ; free virtual = 49627 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 23397 ; free virtual = 49621 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 23398 ; free virtual = 49622 --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 23391 ; free virtual = 49615 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 23349 ; free virtual = 49573 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 23332 ; free virtual = 49556 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 23327 ; free virtual = 49551 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 23343 ; free virtual = 49547 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 23344 ; free virtual = 49548 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading site data... Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 23170 ; free virtual = 49375 Starting Routing Task --------------------------------------------------------------------------------- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 23171 ; free virtual = 49375 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: Helper process launched with PID 20517 --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.570 ; gain = 81.648 ; free physical = 23135 ; free virtual = 49340 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 23129 ; free virtual = 49334 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 23125 ; free virtual = 49330 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 23122 ; free virtual = 49327 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 23121 ; free virtual = 49326 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 23120 ; free virtual = 49324 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 23117 ; free virtual = 49322 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 1350.090 ; gain = 254.160 ; free physical = 23119 ; free virtual = 49323 report_drc (run_mandatory_drcs) completed successfully INFO: [Project 1-571] Translating synthesized netlist INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 23140 ; free virtual = 49344 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1248] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1272] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:27] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1296] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1344] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1368] Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1392] Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1560] Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1584] Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1608] Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1632] Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1656] Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1848] Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2040] INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:139] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2064] Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2280] INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 22877 ; free virtual = 49083 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 22834 ; free virtual = 49040 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 22832 ; free virtual = 49037 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 22809 ; free virtual = 49014 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). No constraint files found. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1843.211 ; gain = 0.000 ; free physical = 22807 ; free virtual = 49013 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 22695 ; free virtual = 48901 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1931.254 ; gain = 467.531 ; free physical = 22653 ; free virtual = 48859 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1931.254 ; gain = 467.531 ; free physical = 22639 ; free virtual = 48844 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1931.254 ; gain = 467.531 ; free physical = 22637 ; free virtual = 48842 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1931.254 ; gain = 467.531 ; free physical = 22636 ; free virtual = 48841 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1931.254 ; gain = 467.531 ; free physical = 22635 ; free virtual = 48840 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1931.254 ; gain = 467.531 ; free physical = 22633 ; free virtual = 48838 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1931.254 ; gain = 533.562 ; free physical = 22632 ; free virtual = 48837 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 22362 ; free virtual = 48568 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 22330 ; free virtual = 48535 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 22327 ; free virtual = 48533 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 22325 ; free virtual = 48530 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 22323 ; free virtual = 48528 Phase 2 Final Placement Cleanup ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 22318 ; free virtual = 48523 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 22316 ; free virtual = 48521 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 22315 ; free virtual = 48520 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-28] Unisim Transformation completed in 3 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Writing bitstream ./design.bit... INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20638 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1338.098 ; gain = 242.184 ; free physical = 22275 ; free virtual = 48484 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 22262 ; free virtual = 48471 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1338.098 ; gain = 242.184 ; free physical = 22196 ; free virtual = 48405 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 22088 ; free virtual = 48297 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:150] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:150] Finished Final Netlist Cleanup WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:155] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:280] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:285] --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 22050 ; free virtual = 48260 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 22046 ; free virtual = 48256 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22044 ; free virtual = 48253 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:55:57 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2474.129 ; gain = 333.105 ; free physical = 22057 ; free virtual = 48266 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:55:57 2019... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 22225 ; free virtual = 48434 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 23017 ; free virtual = 49226 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 23015 ; free virtual = 49225 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 23008 ; free virtual = 49218 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 23006 ; free virtual = 49216 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 22999 ; free virtual = 49208 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 22997 ; free virtual = 49207 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1346.074 ; gain = 250.160 ; free physical = 22996 ; free virtual = 49205 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1346.082 ; gain = 250.160 ; free physical = 22997 ; free virtual = 49207 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22965 ; free virtual = 49175 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22964 ; free virtual = 49173 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22962 ; free virtual = 49172 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22962 ; free virtual = 49171 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22962 ; free virtual = 49171 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22961 ; free virtual = 49170 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22961 ; free virtual = 49170 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22959 ; free virtual = 49169 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 22960 ; free virtual = 49170 touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_005 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:16] INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/top.v:2] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/top.v:2] INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 22760 ; free virtual = 48978 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 22732 ; free virtual = 48965 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 22731 ; free virtual = 48964 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 22743 ; free virtual = 48956 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 22731 ; free virtual = 48945 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.078 ; gain = 230.156 ; free physical = 22549 ; free virtual = 48763 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 22550 ; free virtual = 48763 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: Launching helper process for spawning children vivado processes 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 22580 ; free virtual = 48794 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: Helper process launched with PID 20784 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:83] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 --------------------------------------------------------------------------------- Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 22483 ; free virtual = 48697 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 22488 ; free virtual = 48702 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 22485 ; free virtual = 48698 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 22484 ; free virtual = 48698 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Device 21-403] Loading part xc7z020clg400-1 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 22483 ; free virtual = 48697 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15fdaa0f7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 22483 ; free virtual = 48697 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 22475 ; free virtual = 48688 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:01 . Memory (MB): peak = 1476.832 ; gain = 393.938 ; free physical = 22219 ; free virtual = 48433 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 1334.105 ; gain = 238.184 ; free physical = 22219 ; free virtual = 48432 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 22027 ; free virtual = 48241 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 22073 ; free virtual = 48287 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 21970 ; free virtual = 48184 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1557.863 ; gain = 0.000 ; free physical = 21982 ; free virtual = 48196 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.48 . Memory (MB): peak = 1557.863 ; gain = 0.000 ; free physical = 21942 ; free virtual = 48156 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 21961 ; free virtual = 48175 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 21959 ; free virtual = 48173 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 1339.105 ; gain = 243.184 ; free physical = 21955 ; free virtual = 48169 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 21955 ; free virtual = 48169 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 21955 ; free virtual = 48169 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 21954 ; free virtual = 48168 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 21954 ; free virtual = 48168 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 21953 ; free virtual = 48167 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 21954 ; free virtual = 48168 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.594 ; gain = 269.969 ; free physical = 21955 ; free virtual = 48169 INFO: [Project 1-571] Translating synthesized netlist Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 21936 ; free virtual = 48150 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 1339.105 ; gain = 243.184 ; free physical = 21924 ; free virtual = 48143 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 21885 ; free virtual = 48099 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 21881 ; free virtual = 48095 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21874 ; free virtual = 48088 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 1347.082 ; gain = 251.160 ; free physical = 21830 ; free virtual = 48044 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:55] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:16] INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21830 ; free virtual = 48044 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21835 ; free virtual = 48048 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21839 ; free virtual = 48053 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21841 ; free virtual = 48055 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21843 ; free virtual = 48057 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21844 ; free virtual = 48058 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21845 ; free virtual = 48059 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21854 ; free virtual = 48072 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 21855 ; free virtual = 48073 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 21843 ; free virtual = 48058 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 21839 ; free virtual = 48053 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 21839 ; free virtual = 48053 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 21809 ; free virtual = 48024 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1347.082 ; gain = 251.160 ; free physical = 21790 ; free virtual = 48005 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1347.082 ; gain = 251.160 ; free physical = 21786 ; free virtual = 48001 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1347.082 ; gain = 251.160 ; free physical = 21755 ; free virtual = 47969 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1347.082 ; gain = 251.160 ; free physical = 21747 ; free virtual = 47961 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1347.082 ; gain = 251.160 ; free physical = 21742 ; free virtual = 47956 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1347.082 ; gain = 251.160 ; free physical = 21739 ; free virtual = 47954 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1347.082 ; gain = 251.160 ; free physical = 21738 ; free virtual = 47952 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1347.082 ; gain = 251.160 ; free physical = 21736 ; free virtual = 47951 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1347.090 ; gain = 251.160 ; free physical = 21738 ; free virtual = 47952 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 20884 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 21488 ; free virtual = 47703 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:04 . Memory (MB): peak = 1476.832 ; gain = 393.945 ; free physical = 21518 ; free virtual = 47732 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 21349 ; free virtual = 47563 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 16bd26d57 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 21348 ; free virtual = 47563 INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1558.863 ; gain = 0.000 ; free physical = 21292 ; free virtual = 47510 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 1467.258 ; gain = 384.367 ; free physical = 21315 ; free virtual = 47530 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1558.863 ; gain = 0.000 ; free physical = 21267 ; free virtual = 47481 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 21155 ; free virtual = 47370 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 21066 ; free virtual = 47281 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21038 ; free virtual = 47252 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 21022 ; free virtual = 47237 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1546.961 ; gain = 0.000 ; free physical = 21044 ; free virtual = 47258 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1dac8b64b Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 21038 ; free virtual = 47253 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21038 ; free virtual = 47253 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21038 ; free virtual = 47253 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21038 ; free virtual = 47252 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21038 ; free virtual = 47252 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1546.961 ; gain = 0.000 ; free physical = 21038 ; free virtual = 47252 Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21038 ; free virtual = 47252 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21037 ; free virtual = 47252 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21037 ; free virtual = 47251 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Phase 1.3 Build Placer Netlist Model | Checksum: 2721b1c31 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 21038 ; free virtual = 47253 Phase 1.4 Constrain Clocks/Macros Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21037 ; free virtual = 47251 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 21037 ; free virtual = 47252 Phase 1.4 Constrain Clocks/Macros | Checksum: 2721b1c31 Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 21037 ; free virtual = 47252 Phase 1 Placer Initialization | Checksum: 2721b1c31 Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 21038 ; free virtual = 47252 Phase 2 Global Placement INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 1 Build RT Design | Checksum: ec53b9f2 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.957 ; gain = 41.668 ; free physical = 20903 ; free virtual = 47118 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: ec53b9f2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2075.945 ; gain = 49.656 ; free physical = 20870 ; free virtual = 47084 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: ec53b9f2 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2075.945 ; gain = 49.656 ; free physical = 20869 ; free virtual = 47084 Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2061.926 ; gain = 43.668 ; free physical = 20855 ; free virtual = 47069 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.914 ; gain = 49.656 ; free physical = 20819 ; free virtual = 47033 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.914 ; gain = 49.656 ; free physical = 20819 ; free virtual = 47033 INFO: [Project 1-570] Preparing netlist for logic optimization Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1a9a59a62 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 20806 ; free virtual = 47021 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2077.969 ; gain = 59.711 ; free physical = 20780 ; free virtual = 46995 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 20780 ; free virtual = 46995 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 20776 ; free virtual = 46990 Phase 4 Rip-up And Reroute | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 20775 ; free virtual = 46989 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 20773 ; free virtual = 46988 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 20773 ; free virtual = 46987 Phase 6 Post Hold Fix | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 20773 ; free virtual = 46987 Phase 7 Route finalize Phase 2 Global Placement | Checksum: 26a0424f4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:21 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20763 ; free virtual = 46978 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 3.1 Commit Multi Column Macros | Checksum: 26a0424f4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:21 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20756 ; free virtual = 46971 Phase 3.2 Commit Most Macros & LUTRAMs Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Number of Nodes with overlaps = 0 Phase 7 Route finalize | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 20752 ; free virtual = 46967 Phase 8 Verifying routed nets Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 20750 ; free virtual = 46964 Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1a9a59a62 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2092.375 ; gain = 66.086 ; free physical = 20751 ; free virtual = 46965 Phase 9 Depositing Routes Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22a14ef89 Time (s): cpu = 00:00:22 ; elapsed = 00:00:21 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20750 ; free virtual = 46964 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 3.3 Area Swap Optimization Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 20749 ; free virtual = 46963 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 20748 ; free virtual = 46963 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 20748 ; free virtual = 46963 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 20748 ; free virtual = 46963 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 20747 ; free virtual = 46962 Phase 3.3 Area Swap Optimization | Checksum: 203efcd54 Time (s): cpu = 00:00:22 ; elapsed = 00:00:21 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20746 ; free virtual = 46960 Phase 3.4 Pipeline Register Optimization Phase 7 Route finalize Phase 3.4 Pipeline Register Optimization | Checksum: 1cda42db9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:21 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20781 ; free virtual = 46995 Phase 3.5 Small Shape Detail Placement Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 9 Depositing Routes | Checksum: 1a9a59a62 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2092.375 ; gain = 66.086 ; free physical = 20781 ; free virtual = 46995 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2092.375 ; gain = 66.086 ; free physical = 20815 ; free virtual = 47030 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2131.164 ; gain = 136.891 ; free physical = 20817 ; free virtual = 47031 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2079.969 ; gain = 61.711 ; free physical = 20813 ; free virtual = 47028 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2081.969 ; gain = 63.711 ; free physical = 20812 ; free virtual = 47026 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2081.969 ; gain = 63.711 ; free physical = 20803 ; free virtual = 47018 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2081.969 ; gain = 63.711 ; free physical = 20839 ; free virtual = 47053 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2120.758 ; gain = 134.516 ; free physical = 20838 ; free virtual = 47052 Writing placer database... Writing placer database... Writing XDEF routing. Phase 3.5 Small Shape Detail Placement | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20821 ; free virtual = 47038 Phase 3.6 Re-assign LUT pins Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 3.6 Re-assign LUT pins | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20820 ; free virtual = 47039 Phase 3.7 Pipeline Register Optimization Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2120.758 ; gain = 0.000 ; free physical = 20820 ; free virtual = 47038 Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 3.7 Pipeline Register Optimization | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20818 ; free virtual = 47038 Phase 3 Detail Placement | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20818 ; free virtual = 47037 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Write XDEF Complete: Time (s): cpu = 00:00:00.98 ; elapsed = 00:00:00.50 . Memory (MB): peak = 2131.164 ; gain = 0.000 ; free physical = 20817 ; free virtual = 47037 Phase 4.1 Post Commit Optimization | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20816 ; free virtual = 47036 Phase 4.2 Post Placement Cleanup INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/design.dcp' has been generated. Phase 4.2 Post Placement Cleanup | Checksum: 210f6607b Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Time (s): cpu = 00:00:23 ; elapsed = 00:00:21 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20815 ; free virtual = 47033 Phase 4.3 Placer Reporting INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4.3 Placer Reporting | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20805 ; free virtual = 47023 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20791 ; free virtual = 47010 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 210f6607b Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20778 ; free virtual = 46996 Ending Placer Task | Checksum: 1c8c94742 Time (s): cpu = 00:00:23 ; elapsed = 00:00:22 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 20787 ; free virtual = 47006 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:23 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 20787 ; free virtual = 47006 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.445 ; gain = 60.824 ; free physical = 20643 ; free virtual = 46858 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: e4299e38 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 20397 ; free virtual = 46612 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 9e4a152e Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2056.938 ; gain = 93.668 ; free physical = 20382 ; free virtual = 46598 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 9e4a152e Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2062.926 ; gain = 99.656 ; free physical = 20340 ; free virtual = 46556 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 9e4a152e Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2062.926 ; gain = 99.656 ; free physical = 20341 ; free virtual = 46557 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15dc3536d Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 20242 ; free virtual = 46458 Phase 3 Initial Routing INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 20297 ; free virtual = 46513 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 20305 ; free virtual = 46521 Phase 4 Rip-up And Reroute | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 20305 ; free virtual = 46521 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 20305 ; free virtual = 46520 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 20305 ; free virtual = 46521 Phase 6 Post Hold Fix | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 20306 ; free virtual = 46521 Phase 7 Route finalize Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1963.352 ; gain = 0.000 ; free physical = 20322 ; free virtual = 46537 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 105.711 ; free physical = 20296 ; free virtual = 46512 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2071.980 ; gain = 108.711 ; free physical = 20298 ; free virtual = 46513 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 15dc3536d Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2071.980 ; gain = 108.711 ; free physical = 20297 ; free virtual = 46512 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2071.980 ; gain = 108.711 ; free physical = 20330 ; free virtual = 46546 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:41 . Memory (MB): peak = 2110.770 ; gain = 179.516 ; free physical = 20328 ; free virtual = 46543 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task Writing placer database... Writing XDEF routing. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 20252 ; free virtual = 46469 Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2110.770 ; gain = 0.000 ; free physical = 20248 ; free virtual = 46466 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1cf4d1b03 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 20242 ; free virtual = 46459 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:38 . Memory (MB): peak = 2068.176 ; gain = 44.668 ; free physical = 20238 ; free virtual = 46454 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:38 . Memory (MB): peak = 2074.164 ; gain = 50.656 ; free physical = 20190 ; free virtual = 46406 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:38 . Memory (MB): peak = 2074.164 ; gain = 50.656 ; free physical = 20187 ; free virtual = 46403 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 20104 ; free virtual = 46320 Phase 3 Initial Routing INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Running DRC as a precondition to command write_bitstream INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 20111 ; free virtual = 46326 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 20097 ; free virtual = 46313 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 20092 ; free virtual = 46308 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 20090 ; free virtual = 46305 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 20087 ; free virtual = 46303 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 20084 ; free virtual = 46300 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 20058 ; free virtual = 46274 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 20054 ; free virtual = 46270 Phase 9 Depositing Routes Loading data files... Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 20052 ; free virtual = 46267 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 20092 ; free virtual = 46307 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:41 . Memory (MB): peak = 2128.258 ; gain = 136.766 ; free physical = 20093 ; free virtual = 46309 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2051.395 ; gain = 493.531 ; free physical = 20094 ; free virtual = 46310 Phase 1.3 Build Placer Netlist Model Writing placer database... Loading data files... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2128.258 ; gain = 0.000 ; free physical = 20076 ; free virtual = 46295 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:16] Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 19831 ; free virtual = 46048 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 19766 ; free virtual = 45983 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.980 ; gain = 140.359 ; free physical = 19766 ; free virtual = 45984 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:04 . Memory (MB): peak = 1476.848 ; gain = 393.953 ; free physical = 19279 ; free virtual = 45496 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2051.395 ; gain = 493.531 ; free physical = 19241 ; free virtual = 45458 Phase 1.4 Constrain Clocks/Macros INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2051.395 ; gain = 493.531 ; free physical = 19144 ; free virtual = 45361 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2051.395 ; gain = 493.531 ; free physical = 19068 ; free virtual = 45285 Phase 2 Final Placement Cleanup INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.973 ; gain = 172.352 ; free physical = 19065 ; free virtual = 45282 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2051.395 ; gain = 493.531 ; free physical = 19059 ; free virtual = 45276 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 19073 ; free virtual = 45290 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2051.395 ; gain = 493.531 ; free physical = 19020 ; free virtual = 45237 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2051.395 ; gain = 574.562 ; free physical = 19005 ; free virtual = 45222 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1487277ac Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 18844 ; free virtual = 45061 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 18839 ; free virtual = 45056 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 18838 ; free virtual = 45055 Phase 1 Placer Initialization | Checksum: 1dfc4dd92 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 18837 ; free virtual = 45054 Phase 2 Global Placement report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1559.879 ; gain = 0.000 ; free physical = 18766 ; free virtual = 44983 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.49 . Memory (MB): peak = 1559.879 ; gain = 0.000 ; free physical = 18710 ; free virtual = 44927 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Timing 38-35] Done setting XDC timing constraints. Loading site data... Loading route data... Loading site data... Processing options... Creating bitmap... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Global Placement | Checksum: 1d7ade655 Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17975 ; free virtual = 44192 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1d7ade655 Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17969 ; free virtual = 44186 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 24340a58a Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17959 ; free virtual = 44176 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 17954 ; free virtual = 44171 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21d1b8355 Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17929 ; free virtual = 44146 Phase 3.4 Pipeline Register Optimization Loading route data... Phase 3.4 Pipeline Register Optimization | Checksum: 1e6cfe3ba Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17917 ; free virtual = 44135 Phase 3.5 Small Shape Detail Placement Processing options... Creating bitmap... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.5 Small Shape Detail Placement | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17852 ; free virtual = 44070 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17852 ; free virtual = 44069 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17860 ; free virtual = 44077 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 3 Detail Placement | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17858 ; free virtual = 44075 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17846 ; free virtual = 44063 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17846 ; free virtual = 44063 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17844 ; free virtual = 44061 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17839 ; free virtual = 44056 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1abeaee1f Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17839 ; free virtual = 44056 Ending Placer Task | Checksum: 163bdd4e6 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2100.547 ; gain = 611.582 ; free physical = 17852 ; free virtual = 44069 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2100.547 ; gain = 675.613 ; free physical = 17852 ; free virtual = 44069 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.449 ; gain = 0.000 ; free physical = 17859 ; free virtual = 44076 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 17748 ; free virtual = 43965 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 17753 ; free virtual = 43970 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 7f1e2bdc ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 17757 ; free virtual = 43974 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 17736 ; free virtual = 43953 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.164 ; gain = 456.203 ; free physical = 17725 ; free virtual = 43942 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 17634 ; free virtual = 43851 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 17637 ; free virtual = 43854 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 17626 ; free virtual = 43843 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 17626 ; free virtual = 43843 --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 17626 ; free virtual = 43843 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 17626 ; free virtual = 43843 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 17625 ; free virtual = 43842 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 17626 ; free virtual = 43843 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.590 ; gain = 269.961 ; free physical = 17628 ; free virtual = 43845 INFO: [Project 1-571] Translating synthesized netlist Loading route data... Processing options... Creating bitmap... INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Creating bitstream... INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Creating bitstream... Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.164 ; gain = 456.203 ; free physical = 17326 ; free virtual = 43544 Phase 1.4 Constrain Clocks/Macros Loading site data... Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.164 ; gain = 456.203 ; free physical = 17258 ; free virtual = 43475 INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.164 ; gain = 456.203 ; free physical = 17195 ; free virtual = 43412 Phase 2 Global Placement Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 17117 ; free virtual = 43334 Phase 1.4 Constrain Clocks/Macros Loading route data... Processing options... Creating bitmap... Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 17029 ; free virtual = 43246 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 17028 ; free virtual = 43245 Phase 2 Final Placement Cleanup Creating bitstream... Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 17013 ; free virtual = 43230 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1909.453 ; gain = 0.000 ; free physical = 17010 ; free virtual = 43227 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.395 ; gain = 493.531 ; free physical = 17011 ; free virtual = 43228 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 17005 ; free virtual = 43223 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: f35ea853 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1997.496 ; gain = 508.531 ; free physical = 16938 ; free virtual = 43155 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 18ab10e39 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1997.496 ; gain = 508.531 ; free physical = 16934 ; free virtual = 43151 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 18ab10e39 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1997.496 ; gain = 508.531 ; free physical = 16934 ; free virtual = 43151 Phase 1 Placer Initialization | Checksum: 18ab10e39 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1997.496 ; gain = 508.531 ; free physical = 16932 ; free virtual = 43150 Phase 2 Global Placement Writing bitstream ./design.bit... Writing bitstream ./design.bit... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 17766 ; free virtual = 43995 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 17745 ; free virtual = 43975 Phase 3.2 Commit Most Macros & LUTRAMs WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 17767 ; free virtual = 43997 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 17752 ; free virtual = 43982 Phase 3.4 Pipeline Register Optimization Writing bitstream ./design.bit... Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 17747 ; free virtual = 43980 Phase 3.5 Small Shape Detail Placement INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 2 Global Placement | Checksum: 1829a16fc Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18067 ; free virtual = 44301 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 1829a16fc Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18065 ; free virtual = 44298 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 251526ef8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18065 ; free virtual = 44299 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 22b2d4cc3 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18063 ; free virtual = 44296 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1f4e1ad28 Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18062 ; free virtual = 44295 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 1b65b8b46 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18052 ; free virtual = 44286 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 1b65b8b46 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18052 ; free virtual = 44285 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 1b65b8b46 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18054 ; free virtual = 44287 Phase 3 Detail Placement | Checksum: 1b65b8b46 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18054 ; free virtual = 44287 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 1b65b8b46 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18053 ; free virtual = 44286 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 1b65b8b46 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18054 ; free virtual = 44287 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 1b65b8b46 Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18053 ; free virtual = 44287 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18053 ; free virtual = 44286 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b65b8b46 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18053 ; free virtual = 44286 Ending Placer Task | Checksum: 16e2e720d Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2093.543 ; gain = 604.578 ; free physical = 18064 ; free virtual = 44297 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2093.543 ; gain = 668.609 ; free physical = 18064 ; free virtual = 44297 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 18047 ; free virtual = 44281 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 18045 ; free virtual = 44279 Phase 3.7 Pipeline Register Optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:56:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2454.875 ; gain = 344.105 ; free physical = 18054 ; free virtual = 44287 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:56:59 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:56:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 18093 ; free virtual = 44326 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:33 . Memory (MB): peak = 2460.863 ; gain = 340.105 ; free physical = 18110 ; free virtual = 44344 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:56:59 2019... Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 18485 ; free virtual = 44718 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:57:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. DONE WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:33 . Memory (MB): peak = 2471.270 ; gain = 340.105 ; free physical = 19862 ; free virtual = 46095 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:57:00 2019... Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Bitstream size: 4243411 bytes Checksum: PlaceDB: 898ec903 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design Config size: 1060815 words Number of configuration frames: 9996 touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 20031 ; free virtual = 46264 DONE Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 20082 ; free virtual = 46315 Phase 4.3 Placer Reporting touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_005 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 20907 ; free virtual = 47142 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 20837 ; free virtual = 47071 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:57:00 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2472.363 ; gain = 344.105 ; free physical = 20847 ; free virtual = 47082 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:57:00 2019... INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_005 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 20887 ; free virtual = 47123 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 1468.254 ; gain = 385.359 ; free physical = 20914 ; free virtual = 47149 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.207 ; gain = 544.246 ; free physical = 21840 ; free virtual = 48076 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2091.207 ; gain = 623.949 ; free physical = 21856 ; free virtual = 48092 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_006 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1549.957 ; gain = 0.000 ; free physical = 21637 ; free virtual = 47873 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.41 . Memory (MB): peak = 1549.957 ; gain = 0.000 ; free physical = 21662 ; free virtual = 47898 INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1964.367 ; gain = 0.000 ; free physical = 21589 ; free virtual = 47825 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 2052.410 ; gain = 492.531 ; free physical = 21492 ; free virtual = 47735 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.410 ; gain = 492.531 ; free physical = 21249 ; free virtual = 47485 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.410 ; gain = 492.531 ; free physical = 21245 ; free virtual = 47481 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.410 ; gain = 492.531 ; free physical = 21240 ; free virtual = 47476 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.410 ; gain = 492.531 ; free physical = 21230 ; free virtual = 47466 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.410 ; gain = 492.531 ; free physical = 21267 ; free virtual = 47503 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:34 . Memory (MB): peak = 2052.410 ; gain = 575.562 ; free physical = 21227 ; free virtual = 47463 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: ff03af09 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 21045 ; free virtual = 47281 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Starting Routing Task Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: ff03af09 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 21028 ; free virtual = 47264 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: ff03af09 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 21027 ; free virtual = 47263 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b4ae2ab4 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20957 ; free virtual = 47194 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 130e541f3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20952 ; free virtual = 47188 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20952 ; free virtual = 47188 Phase 4 Rip-up And Reroute | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20952 ; free virtual = 47188 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20954 ; free virtual = 47190 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20954 ; free virtual = 47190 Phase 6 Post Hold Fix | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20954 ; free virtual = 47190 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20946 ; free virtual = 47182 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20946 ; free virtual = 47182 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 130e541f3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20941 ; free virtual = 47177 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2101.230 ; gain = 8.684 ; free physical = 20977 ; free virtual = 47213 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2140.020 ; gain = 47.473 ; free physical = 20977 ; free virtual = 47213 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2140.020 ; gain = 0.000 ; free physical = 20968 ; free virtual = 47206 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Timing 38-35] Done setting XDC timing constraints. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.445 ; gain = 0.000 ; free physical = 20139 ; free virtual = 46376 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24678 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24684 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24757 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 24798 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 2003.160 ; gain = 453.203 ; free physical = 19948 ; free virtual = 46185 Phase 1.3 Build Placer Netlist Model Phase 1 Build RT Design | Checksum: 168520de7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.078 ; gain = 52.668 ; free physical = 19903 ; free virtual = 46140 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 168520de7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2145.066 ; gain = 61.656 ; free physical = 19850 ; free virtual = 46087 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 168520de7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2145.066 ; gain = 61.656 ; free physical = 19850 ; free virtual = 46087 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15eed57fc Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 19785 ; free virtual = 46022 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:44 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 19765 ; free virtual = 46001 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 19764 ; free virtual = 46001 Phase 4 Rip-up And Reroute | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 19762 ; free virtual = 45999 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 19762 ; free virtual = 45999 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 19762 ; free virtual = 45999 Phase 6 Post Hold Fix | Checksum: 15eed57fc Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 19762 ; free virtual = 45999 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 19758 ; free virtual = 45995 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 19759 ; free virtual = 45996 Phase 9 Depositing Routes Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.160 ; gain = 453.203 ; free physical = 19740 ; free virtual = 45976 Phase 1.4 Constrain Clocks/Macros Phase 9 Depositing Routes | Checksum: 15eed57fc Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 19739 ; free virtual = 45976 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.496 ; gain = 96.086 ; free physical = 19783 ; free virtual = 46019 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:48 . Memory (MB): peak = 2218.285 ; gain = 166.891 ; free physical = 19783 ; free virtual = 46019 Phase 1 Build RT Design | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.547 ; gain = 0.000 ; free physical = 19783 ; free virtual = 46020 Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.160 ; gain = 453.203 ; free physical = 19782 ; free virtual = 46019 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.547 ; gain = 0.000 ; free physical = 19751 ; free virtual = 45988 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1bc3b0b65 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.547 ; gain = 0.000 ; free physical = 19751 ; free virtual = 45988 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.160 ; gain = 453.203 ; free physical = 19734 ; free virtual = 45971 Phase 2 Global Placement Writing placer database... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 100878403 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2101.227 ; gain = 0.680 ; free physical = 19725 ; free virtual = 45968 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: e4c05920 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2101.227 ; gain = 0.680 ; free physical = 19719 ; free virtual = 45967 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: e4c05920 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2101.227 ; gain = 0.680 ; free physical = 19717 ; free virtual = 45964 Phase 4 Rip-up And Reroute | Checksum: e4c05920 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2101.227 ; gain = 0.680 ; free physical = 19717 ; free virtual = 45964 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: e4c05920 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2101.227 ; gain = 0.680 ; free physical = 19715 ; free virtual = 45964 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: e4c05920 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2101.227 ; gain = 0.680 ; free physical = 19715 ; free virtual = 45964 Phase 6 Post Hold Fix | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2101.227 ; gain = 0.680 ; free physical = 19707 ; free virtual = 45955 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2101.227 ; gain = 0.680 ; free physical = 19698 ; free virtual = 45947 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2101.227 ; gain = 0.680 ; free physical = 19695 ; free virtual = 45944 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: e4c05920 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2101.227 ; gain = 0.680 ; free physical = 19681 ; free virtual = 45931 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2101.227 ; gain = 0.680 ; free physical = 19716 ; free virtual = 45967 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2140.016 ; gain = 39.469 ; free physical = 19716 ; free virtual = 45966 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.30 . Memory (MB): peak = 2140.016 ; gain = 0.000 ; free physical = 19673 ; free virtual = 45927 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Loading route data... Processing options... Creating bitmap... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2218.285 ; gain = 0.000 ; free physical = 19531 ; free virtual = 45796 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 19535 ; free virtual = 45801 --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19532 ; free virtual = 45798 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/design.dcp' has been generated. Command: write_bitstream -force design.bit Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19678 ; free virtual = 45919 Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19627 ; free virtual = 45868 --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 19599 ; free virtual = 45840 --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 19601 ; free virtual = 45841 --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19599 ; free virtual = 45839 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19603 ; free virtual = 45843 Phase 3.5 Small Shape Detail Placement Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 19601 ; free virtual = 45842 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 19619 ; free virtual = 45859 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 19600 ; free virtual = 45841 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 19598 ; free virtual = 45839 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 19553 ; free virtual = 45794 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3108] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3938] INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3964] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:68] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4065] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:83] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4480] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:88] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4646] INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4729] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:103] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4812] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:273] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4895] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:293] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:4978] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:313] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5061] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:328] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5144] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:398] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5227] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:408] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5310] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:413] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:418] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5476] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:423] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5559] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:428] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5642] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:433] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5725] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:443] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6140] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/top.v:2] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19435 ; free virtual = 45680 Phase 3.6 Re-assign LUT pins --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 19421 ; free virtual = 45662 --------------------------------------------------------------------------------- Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19402 ; free virtual = 45644 Phase 3.7 Pipeline Register Optimization --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 19399 ; free virtual = 45641 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 19399 ; free virtual = 45640 --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/top.v:2] Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19410 ; free virtual = 45652 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 19414 ; free virtual = 45656 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Loading data files... Phase 1 Build RT Design | Checksum: 1a631b8be Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2134.078 ; gain = 49.668 ; free physical = 19452 ; free virtual = 45695 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19445 ; free virtual = 45694 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 19430 ; free virtual = 45672 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:36] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:267] Phase 4.1 Post Commit Optimization | Checksum: 181723f81 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:295] Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19434 ; free virtual = 45676 WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:610] Phase 4.2 Post Placement Cleanup WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/top.v:2] Phase 2.1 Fix Topology Constraints | Checksum: 1a631b8be Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2144.066 ; gain = 59.656 ; free physical = 19379 ; free virtual = 45629 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1a631b8be Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2144.066 ; gain = 59.656 ; free physical = 19377 ; free virtual = 45627 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 19380 ; free virtual = 45622 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 19381 ; free virtual = 45622 --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19388 ; free virtual = 45630 Phase 4.3 Placer Reporting INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 19394 ; free virtual = 45637 --------------------------------------------------------------------------------- Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19379 ; free virtual = 45621 Phase 4.4 Final Placement Cleanup --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 19372 ; free virtual = 45614 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 19371 ; free virtual = 45613 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19332 ; free virtual = 45574 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 19318 ; free virtual = 45560 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 19318 ; free virtual = 45560 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19282 ; free virtual = 45524 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.207 ; gain = 549.250 ; free physical = 19282 ; free virtual = 45524 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.207 ; gain = 630.953 ; free physical = 19281 ; free virtual = 45523 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Router Initialization | Checksum: 18b270a8f Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2178.496 ; gain = 94.086 ; free physical = 19277 ; free virtual = 45519 Phase 3 Initial Routing Creating bitstream... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18b270a8f Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2178.496 ; gain = 94.086 ; free physical = 19116 ; free virtual = 45358 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18b270a8f Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2178.496 ; gain = 94.086 ; free physical = 19106 ; free virtual = 45348 Phase 4 Rip-up And Reroute | Checksum: 18b270a8f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2178.496 ; gain = 94.086 ; free physical = 19104 ; free virtual = 45346 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18b270a8f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2178.496 ; gain = 94.086 ; free physical = 19101 ; free virtual = 45343 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18b270a8f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2178.496 ; gain = 94.086 ; free physical = 19099 ; free virtual = 45341 Phase 6 Post Hold Fix | Checksum: 18b270a8f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2178.496 ; gain = 94.086 ; free physical = 19096 ; free virtual = 45338 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18b270a8f Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2178.496 ; gain = 94.086 ; free physical = 19100 ; free virtual = 45342 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18b270a8f Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2178.496 ; gain = 94.086 ; free physical = 19095 ; free virtual = 45337 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 18b270a8f Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2178.496 ; gain = 94.086 ; free physical = 19078 ; free virtual = 45320 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2178.496 ; gain = 94.086 ; free physical = 19121 ; free virtual = 45363 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:45 . Memory (MB): peak = 2217.285 ; gain = 164.891 ; free physical = 19121 ; free virtual = 45363 Writing placer database... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 1e03090e9 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2093.543 ; gain = 0.000 ; free physical = 19113 ; free virtual = 45381 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1e03090e9 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2093.543 ; gain = 0.000 ; free physical = 19053 ; free virtual = 45322 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1e03090e9 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2093.543 ; gain = 0.000 ; free physical = 19051 ; free virtual = 45320 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 19059 ; free virtual = 45328 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 19057 ; free virtual = 45327 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 19084 ; free virtual = 45354 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2217.285 ; gain = 0.000 ; free physical = 19073 ; free virtual = 45347 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 129e3aa92 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2102.227 ; gain = 8.684 ; free physical = 19018 ; free virtual = 45292 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 8.684 ; free physical = 19022 ; free virtual = 45297 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 8.684 ; free physical = 19016 ; free virtual = 45291 Phase 4 Rip-up And Reroute | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 8.684 ; free physical = 19015 ; free virtual = 45290 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 8.684 ; free physical = 19014 ; free virtual = 45290 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 8.684 ; free physical = 19011 ; free virtual = 45287 Phase 6 Post Hold Fix | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 8.684 ; free physical = 19011 ; free virtual = 45287 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 8.684 ; free physical = 18971 ; free virtual = 45248 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 8.684 ; free physical = 18967 ; free virtual = 45244 Phase 9 Depositing Routes INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18996 ; free virtual = 45245 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18995 ; free virtual = 45244 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18993 ; free virtual = 45242 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18991 ; free virtual = 45240 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18990 ; free virtual = 45239 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18989 ; free virtual = 45239 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18987 ; free virtual = 45237 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Phase 9 Depositing Routes | Checksum: b51bc211 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 8.684 ; free physical = 18983 ; free virtual = 45236 Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 18987 ; free virtual = 45240 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 19007 ; free virtual = 45260 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2102.227 ; gain = 8.684 ; free physical = 19017 ; free virtual = 45270 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2141.016 ; gain = 47.473 ; free physical = 19014 ; free virtual = 45268 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2141.016 ; gain = 0.000 ; free physical = 18960 ; free virtual = 45211 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 18953 ; free virtual = 45205 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 18950 ; free virtual = 45200 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18941 ; free virtual = 45191 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.684 ; gain = 215.238 ; free physical = 18905 ; free virtual = 45155 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream INFO: [Project 1-570] Preparing netlist for logic optimization Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:57:44 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Running DRC as a precondition to command write_bitstream 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:28 . Memory (MB): peak = 2475.125 ; gain = 335.105 ; free physical = 18927 ; free virtual = 45177 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:57:44 2019... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2129.438 ; gain = 38.230 ; free physical = 18920 ; free virtual = 45170 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.684 ; gain = 215.238 ; free physical = 18920 ; free virtual = 45170 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 18882 ; free virtual = 45131 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2135.426 ; gain = 44.219 ; free physical = 18884 ; free virtual = 45134 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2135.426 ; gain = 44.219 ; free physical = 18885 ; free virtual = 45134 --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18880 ; free virtual = 45130 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18896 ; free virtual = 45146 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18901 ; free virtual = 45151 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18900 ; free virtual = 45150 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18899 ; free virtual = 45149 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18906 ; free virtual = 45156 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18913 ; free virtual = 45163 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18933 ; free virtual = 45183 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 19145 ; free virtual = 45395 INFO: [Project 1-571] Translating synthesized netlist Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.922 ; gain = 211.484 ; free physical = 19717 ; free virtual = 45966 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1306.922 ; gain = 211.484 ; free physical = 19694 ; free virtual = 45943 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2153.480 ; gain = 62.273 ; free physical = 19697 ; free virtual = 45946 Phase 3 Initial Routing Loading site data... touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1314.898 ; gain = 219.461 ; free physical = 19707 ; free virtual = 45957 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2153.480 ; gain = 62.273 ; free physical = 19699 ; free virtual = 45948 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2153.480 ; gain = 62.273 ; free physical = 19682 ; free virtual = 45932 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2153.480 ; gain = 62.273 ; free physical = 19682 ; free virtual = 45932 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2153.480 ; gain = 62.273 ; free physical = 19681 ; free virtual = 45931 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2153.480 ; gain = 62.273 ; free physical = 19680 ; free virtual = 45930 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2153.480 ; gain = 62.273 ; free physical = 19680 ; free virtual = 45930 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 19661 ; free virtual = 45911 --------------------------------------------------------------------------------- Loading route data... Phase 7 Route finalize Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 19649 ; free virtual = 45899 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 19643 ; free virtual = 45892 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 19642 ; free virtual = 45891 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Processing options... Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 19640 ; free virtual = 45889 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Creating bitmap... Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2153.480 ; gain = 62.273 ; free physical = 19613 ; free virtual = 45863 Phase 8 Verifying routed nets Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2153.480 ; gain = 62.273 ; free physical = 19610 ; free virtual = 45860 Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 19610 ; free virtual = 45860 Phase 9 Depositing Routes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 19599 ; free virtual = 45850 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2153.480 ; gain = 62.273 ; free physical = 19595 ; free virtual = 45846 Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.676 ; gain = 225.230 ; free physical = 19620 ; free virtual = 45870 INFO: [Route 35-16] Router Completed Successfully Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.684 ; gain = 225.230 ; free physical = 19627 ; free virtual = 45877 Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2153.480 ; gain = 62.273 ; free physical = 19627 ; free virtual = 45877 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:45 . Memory (MB): peak = 2192.270 ; gain = 101.062 ; free physical = 19626 ; free virtual = 45876 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Writing placer database... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.898 ; gain = 219.461 ; free physical = 19510 ; free virtual = 45763 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.898 ; gain = 219.461 ; free physical = 19512 ; free virtual = 45766 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.898 ; gain = 219.461 ; free physical = 19544 ; free virtual = 45798 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.898 ; gain = 219.461 ; free physical = 19540 ; free virtual = 45794 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.898 ; gain = 219.461 ; free physical = 19533 ; free virtual = 45787 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.898 ; gain = 219.461 ; free physical = 19533 ; free virtual = 45787 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.898 ; gain = 219.461 ; free physical = 19532 ; free virtual = 45786 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.898 ; gain = 219.461 ; free physical = 19528 ; free virtual = 45782 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.906 ; gain = 219.461 ; free physical = 19529 ; free virtual = 45783 INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-571] Translating synthesized netlist INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 19447 ; free virtual = 45707 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1464.719 ; gain = 0.000 ; free physical = 19315 ; free virtual = 45583 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1464.719 ; gain = 0.000 ; free physical = 19316 ; free virtual = 45584 Loading data files... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2192.270 ; gain = 0.000 ; free physical = 19268 ; free virtual = 45541 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2192.270 ; gain = 0.000 ; free physical = 19191 ; free virtual = 45443 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1405.676 ; gain = 322.789 ; free physical = 19113 ; free virtual = 45366 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.707 ; gain = 0.000 ; free physical = 18896 ; free virtual = 45148 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1470.707 ; gain = 0.000 ; free physical = 18894 ; free virtual = 45146 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1406.914 ; gain = 324.031 ; free physical = 18926 ; free virtual = 45178 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Loading site data... 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 18824 ; free virtual = 45076 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Starting Placer Task Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1472.945 ; gain = 0.000 ; free physical = 18761 ; free virtual = 45013 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1472.945 ; gain = 0.000 ; free physical = 18771 ; free virtual = 45023 Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1483.738 ; gain = 0.000 ; free physical = 18950 ; free virtual = 45206 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1483.738 ; gain = 0.000 ; free physical = 18934 ; free virtual = 45190 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Build RT Design | Checksum: 1577c780a Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2135.094 ; gain = 50.668 ; free physical = 18956 ; free virtual = 45212 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1577c780a Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2145.082 ; gain = 60.656 ; free physical = 18816 ; free virtual = 45072 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1577c780a Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2145.082 ; gain = 60.656 ; free physical = 18828 ; free virtual = 45084 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Number of Nodes with overlaps = 0 Loading data files... Phase 2 Router Initialization | Checksum: 17ae0cba6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2180.512 ; gain = 96.086 ; free physical = 18773 ; free virtual = 45029 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.512 ; gain = 96.086 ; free physical = 18724 ; free virtual = 44980 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.512 ; gain = 96.086 ; free physical = 18716 ; free virtual = 44972 Phase 4 Rip-up And Reroute | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.512 ; gain = 96.086 ; free physical = 18715 ; free virtual = 44971 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.512 ; gain = 96.086 ; free physical = 18711 ; free virtual = 44967 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.512 ; gain = 96.086 ; free physical = 18710 ; free virtual = 44966 Phase 6 Post Hold Fix | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.512 ; gain = 96.086 ; free physical = 18708 ; free virtual = 44964 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.512 ; gain = 96.086 ; free physical = 18691 ; free virtual = 44947 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 17ae0cba6 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.512 ; gain = 96.086 ; free physical = 18682 ; free virtual = 44938 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 17ae0cba6 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.512 ; gain = 96.086 ; free physical = 18567 ; free virtual = 44823 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.512 ; gain = 96.086 ; free physical = 18603 ; free virtual = 44860 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 2219.301 ; gain = 166.891 ; free physical = 18603 ; free virtual = 44859 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:58:01 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:32 . Memory (MB): peak = 2474.121 ; gain = 334.105 ; free physical = 18590 ; free virtual = 44846 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:58:01 2019... Writing placer database... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading site data... touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_006 Loading route data... Processing options... Creating bitmap... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2219.301 ; gain = 0.000 ; free physical = 19270 ; free virtual = 45555 Creating bitstream... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2219.301 ; gain = 0.000 ; free physical = 19251 ; free virtual = 45511 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... Loading site data... Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading site data... Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 25962 Creating bitstream... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 18805 ; free virtual = 45069 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing bitstream ./design.bit... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_003/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:58:14 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:03 ; elapsed = 00:00:43 . Memory (MB): peak = 2607.445 ; gain = 389.160 ; free physical = 18807 ; free virtual = 45075 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:58:14 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.250 ; gain = 467.531 ; free physical = 20161 ; free virtual = 46428 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.250 ; gain = 467.531 ; free physical = 20157 ; free virtual = 46424 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.250 ; gain = 467.531 ; free physical = 20157 ; free virtual = 46424 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.250 ; gain = 467.531 ; free physical = 20157 ; free virtual = 46424 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.250 ; gain = 467.531 ; free physical = 20157 ; free virtual = 46424 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1932.250 ; gain = 467.531 ; free physical = 20157 ; free virtual = 46424 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 20157 ; free virtual = 46424 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_003/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.195 ; gain = 0.000 ; free physical = 19840 ; free virtual = 46112 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 19908 ; free virtual = 46180 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 19814 ; free virtual = 46087 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 19799 ; free virtual = 46071 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 19779 ; free virtual = 46051 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 19771 ; free virtual = 46043 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1986.238 ; gain = 515.531 ; free physical = 19793 ; free virtual = 46065 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:26 . Memory (MB): peak = 1986.238 ; gain = 580.562 ; free physical = 19792 ; free virtual = 46064 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:58:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:36 . Memory (MB): peak = 2475.121 ; gain = 334.105 ; free physical = 19793 ; free virtual = 46066 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:58:19 2019... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1903.434 ; gain = 0.000 ; free physical = 19820 ; free virtual = 46092 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.477 ; gain = 518.531 ; free physical = 20721 ; free virtual = 46993 Phase 1.3 Build Placer Netlist Model Starting Routing Task touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_010 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.477 ; gain = 518.531 ; free physical = 20691 ; free virtual = 46964 Phase 1.4 Constrain Clocks/Macros Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.477 ; gain = 518.531 ; free physical = 20648 ; free virtual = 46920 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.477 ; gain = 518.531 ; free physical = 20615 ; free virtual = 46888 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.477 ; gain = 518.531 ; free physical = 20589 ; free virtual = 46862 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.477 ; gain = 518.531 ; free physical = 20556 ; free virtual = 46829 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.477 ; gain = 584.562 ; free physical = 20546 ; free virtual = 46819 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.227 ; gain = 0.000 ; free physical = 20358 ; free virtual = 46631 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 20404 ; free virtual = 46677 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 20389 ; free virtual = 46663 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 20380 ; free virtual = 46653 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 20353 ; free virtual = 46626 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 20360 ; free virtual = 46633 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1994.270 ; gain = 510.531 ; free physical = 20393 ; free virtual = 46666 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1994.270 ; gain = 577.562 ; free physical = 20393 ; free virtual = 46666 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:58:21 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2532.375 ; gain = 340.105 ; free physical = 20348 ; free virtual = 46621 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:58:22 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_011 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 21337 ; free virtual = 47610 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 21398 ; free virtual = 47676 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 21404 ; free virtual = 47683 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 21404 ; free virtual = 47683 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2130.434 ; gain = 31.227 ; free physical = 21396 ; free virtual = 47674 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2136.422 ; gain = 37.215 ; free physical = 21361 ; free virtual = 47639 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2136.422 ; gain = 37.215 ; free physical = 21361 ; free virtual = 47639 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 21318 ; free virtual = 47596 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 21244 ; free virtual = 47522 Phase 3 Initial Routing Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 21180 ; free virtual = 47458 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 21175 ; free virtual = 47453 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 21175 ; free virtual = 47453 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 21175 ; free virtual = 47452 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 21175 ; free virtual = 47452 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 21175 ; free virtual = 47452 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 21154 ; free virtual = 47432 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 21153 ; free virtual = 47431 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 21153 ; free virtual = 47431 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:48 . Memory (MB): peak = 2154.477 ; gain = 55.270 ; free physical = 21186 ; free virtual = 47464 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:50 . Memory (MB): peak = 2193.266 ; gain = 94.059 ; free physical = 21186 ; free virtual = 47463 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26343 Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_004/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:58:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:45 . Memory (MB): peak = 2606.406 ; gain = 389.121 ; free physical = 21176 ; free virtual = 47460 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:58:28 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_004/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_006 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.266 ; gain = 0.000 ; free physical = 21881 ; free virtual = 48181 Loading site data... Loading route data... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Processing options... Creating bitmap... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 21745 ; free virtual = 48029 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 21724 ; free virtual = 48008 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 21716 ; free virtual = 48001 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 21697 ; free virtual = 47981 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 21697 ; free virtual = 47981 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 21693 ; free virtual = 47977 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 21692 ; free virtual = 47976 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 21690 ; free virtual = 47974 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 21688 ; free virtual = 47972 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 21687 ; free virtual = 47971 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 21682 ; free virtual = 47967 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.688 ; gain = 225.230 ; free physical = 21682 ; free virtual = 47967 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 21353 ; free virtual = 47637 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Project 1-570] Preparing netlist for logic optimization Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:48] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:298] INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 21306 ; free virtual = 47591 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26489 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 21306 ; free virtual = 47591 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 21307 ; free virtual = 47592 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 21301 ; free virtual = 47586 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26532 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 21011 ; free virtual = 47296 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Writing bitstream ./design.bit... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 21229 ; free virtual = 47518 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 21253 ; free virtual = 47542 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26606 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:58:48 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Loading site data... 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:41 . Memory (MB): peak = 2608.422 ; gain = 389.121 ; free physical = 20955 ; free virtual = 47244 --------------------------------------------------------------------------------- INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:58:48 2019... Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 20957 ; free virtual = 47245 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 21015 ; free virtual = 47303 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 21031 ; free virtual = 47319 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 22007 ; free virtual = 48295 --------------------------------------------------------------------------------- touch build/specimen_005/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 21988 ; free virtual = 48277 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 21986 ; free virtual = 48275 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 21981 ; free virtual = 48270 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 21980 ; free virtual = 48269 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 21980 ; free virtual = 48269 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 21980 ; free virtual = 48268 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 21980 ; free virtual = 48268 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 21978 ; free virtual = 48267 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 21980 ; free virtual = 48269 INFO: [Project 1-571] Translating synthesized netlist ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer Creating bitstream... INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4729] INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:5974] INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:426] INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 21864 ; free virtual = 48167 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 21865 ; free virtual = 48160 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 21854 ; free virtual = 48149 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 21853 ; free virtual = 48148 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 21780 ; free virtual = 48074 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 26708 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing bitstream ./design.bit... WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 21782 ; free virtual = 48081 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 21935 ; free virtual = 48234 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 21939 ; free virtual = 48238 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1210.957 ; gain = 115.508 ; free physical = 21964 ; free virtual = 48263 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 21903 ; free virtual = 48202 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 21899 ; free virtual = 48198 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 21832 ; free virtual = 48131 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 21832 ; free virtual = 48131 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1819] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:7] INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:58:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/top.v:2] 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 2532.371 ; gain = 339.105 ; free physical = 21829 ; free virtual = 48128 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:58:56 2019... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 21879 ; free virtual = 48178 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 21967 ; free virtual = 48266 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 21971 ; free virtual = 48270 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1210.953 ; gain = 115.508 ; free physical = 22864 ; free virtual = 49163 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_006 Phase 1 Build RT Design | Checksum: f351153a Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 22738 ; free virtual = 49038 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f351153a Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 22697 ; free virtual = 48996 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f351153a Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2062.922 ; gain = 98.656 ; free physical = 22697 ; free virtual = 48996 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f675539e Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 22659 ; free virtual = 48958 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f675539e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 22728 ; free virtual = 49028 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f675539e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 22726 ; free virtual = 49026 Phase 4 Rip-up And Reroute | Checksum: f675539e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 22726 ; free virtual = 49026 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f675539e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 22725 ; free virtual = 49026 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f675539e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 22725 ; free virtual = 49026 Phase 6 Post Hold Fix | Checksum: f675539e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 22725 ; free virtual = 49026 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 22716 ; free virtual = 49016 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 22716 ; free virtual = 49016 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f675539e Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 22718 ; free virtual = 49018 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2072.977 ; gain = 108.711 ; free physical = 22753 ; free virtual = 49053 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2111.766 ; gain = 179.516 ; free physical = 22755 ; free virtual = 49055 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2111.766 ; gain = 0.000 ; free physical = 22711 ; free virtual = 49014 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 22666 ; free virtual = 48966 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2062.922 ; gain = 44.668 ; free physical = 22641 ; free virtual = 48942 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.910 ; gain = 49.656 ; free physical = 22582 ; free virtual = 48882 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.910 ; gain = 49.656 ; free physical = 22581 ; free virtual = 48882 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 22619 ; free virtual = 48919 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22602 ; free virtual = 48903 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2078.965 ; gain = 60.711 ; free physical = 22586 ; free virtual = 48886 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 22505 ; free virtual = 48806 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 22543 ; free virtual = 48843 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 22536 ; free virtual = 48836 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 22536 ; free virtual = 48836 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 22536 ; free virtual = 48836 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 22526 ; free virtual = 48826 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.965 ; gain = 62.711 ; free physical = 22479 ; free virtual = 48780 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.965 ; gain = 64.711 ; free physical = 22477 ; free virtual = 48777 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.965 ; gain = 64.711 ; free physical = 22516 ; free virtual = 48816 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.965 ; gain = 64.711 ; free physical = 22551 ; free virtual = 48851 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2121.754 ; gain = 135.516 ; free physical = 22551 ; free virtual = 48851 Writing placer database... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22471 ; free virtual = 48774 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22470 ; free virtual = 48774 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Write XDEF Complete: Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2121.754 ; gain = 0.000 ; free physical = 22469 ; free virtual = 48773 --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22469 ; free virtual = 48772 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22469 ; free virtual = 48772 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22469 ; free virtual = 48772 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22468 ; free virtual = 48772 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22468 ; free virtual = 48771 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 22522 ; free virtual = 48825 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 22522 ; free virtual = 48825 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 22435 ; free virtual = 48736 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2066.160 ; gain = 42.668 ; free physical = 22339 ; free virtual = 48640 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2072.148 ; gain = 48.656 ; free physical = 22284 ; free virtual = 48585 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2072.148 ; gain = 48.656 ; free physical = 22281 ; free virtual = 48582 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1331.922 ; gain = 236.473 ; free physical = 22269 ; free virtual = 48570 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22303 ; free virtual = 48604 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 22275 ; free virtual = 48576 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2083.453 ; gain = 59.961 ; free physical = 22156 ; free virtual = 48457 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.453 ; gain = 62.961 ; free physical = 22107 ; free virtual = 48408 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.453 ; gain = 62.961 ; free physical = 22098 ; free virtual = 48399 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.453 ; gain = 62.961 ; free physical = 22098 ; free virtual = 48399 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.453 ; gain = 62.961 ; free physical = 22094 ; free virtual = 48395 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.453 ; gain = 62.961 ; free physical = 22089 ; free virtual = 48390 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.453 ; gain = 62.961 ; free physical = 22089 ; free virtual = 48390 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Timing 38-35] Done setting XDC timing constraints. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.453 ; gain = 62.961 ; free physical = 22063 ; free virtual = 48364 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.453 ; gain = 65.961 ; free physical = 22059 ; free virtual = 48360 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.453 ; gain = 65.961 ; free physical = 22034 ; free virtual = 48335 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.453 ; gain = 65.961 ; free physical = 22073 ; free virtual = 48374 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2128.242 ; gain = 136.766 ; free physical = 22071 ; free virtual = 48372 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 22053 ; free virtual = 48354 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22049 ; free virtual = 48350 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22044 ; free virtual = 48345 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22044 ; free virtual = 48345 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22042 ; free virtual = 48343 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22040 ; free virtual = 48341 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22039 ; free virtual = 48340 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22037 ; free virtual = 48338 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.938 ; gain = 246.488 ; free physical = 22036 ; free virtual = 48337 Writing placer database... Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.945 ; gain = 246.488 ; free physical = 22031 ; free virtual = 48332 INFO: [Project 1-571] Translating synthesized netlist Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2128.242 ; gain = 0.000 ; free physical = 22030 ; free virtual = 48335 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 22023 ; free virtual = 48328 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 22009 ; free virtual = 48311 Phase 1.4 Constrain Clocks/Macros INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 22002 ; free virtual = 48304 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 21985 ; free virtual = 48287 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 21967 ; free virtual = 48269 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 21946 ; free virtual = 48248 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 21942 ; free virtual = 48244 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2] WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1 Build RT Design | Checksum: 1090b26a2 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.953 ; gain = 43.668 ; free physical = 21931 ; free virtual = 48233 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:120] Phase 2.1 Fix Topology Constraints WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:240] Phase 2.1 Fix Topology Constraints | Checksum: 1090b26a2 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2076.941 ; gain = 50.656 ; free physical = 21862 ; free virtual = 48164 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1090b26a2 Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2076.941 ; gain = 50.656 ; free physical = 21860 ; free virtual = 48161 WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1488] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 11706d75b Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 21872 ; free virtual = 48173 Phase 3 Initial Routing INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2090.371 ; gain = 64.086 ; free physical = 21839 ; free virtual = 48140 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2090.371 ; gain = 64.086 ; free physical = 21827 ; free virtual = 48129 Phase 4 Rip-up And Reroute | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2090.371 ; gain = 64.086 ; free physical = 21824 ; free virtual = 48126 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2090.371 ; gain = 64.086 ; free physical = 21820 ; free virtual = 48122 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2090.371 ; gain = 64.086 ; free physical = 21814 ; free virtual = 48116 Phase 6 Post Hold Fix | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2090.371 ; gain = 64.086 ; free physical = 21811 ; free virtual = 48112 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 21788 ; free virtual = 48089 --------------------------------------------------------------------------------- Phase 7 Route finalize | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2090.371 ; gain = 64.086 ; free physical = 21787 ; free virtual = 48089 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 11706d75b Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2093.371 ; gain = 67.086 ; free physical = 21786 ; free virtual = 48087 Phase 9 Depositing Routes report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 9 Depositing Routes | Checksum: 11706d75b Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2093.371 ; gain = 67.086 ; free physical = 21776 ; free virtual = 48078 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2093.371 ; gain = 67.086 ; free physical = 21813 ; free virtual = 48115 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2132.160 ; gain = 137.891 ; free physical = 21813 ; free virtual = 48115 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1331.918 ; gain = 236.473 ; free physical = 21775 ; free virtual = 48076 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Writing placer database... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21739 ; free virtual = 48042 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.59 . Memory (MB): peak = 2132.160 ; gain = 0.000 ; free physical = 21678 ; free virtual = 47983 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21456 ; free virtual = 47759 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21461 ; free virtual = 47764 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21467 ; free virtual = 47769 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21468 ; free virtual = 47770 --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21470 ; free virtual = 47772 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21470 ; free virtual = 47773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21472 ; free virtual = 47775 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.934 ; gain = 246.488 ; free physical = 21480 ; free virtual = 47782 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 21481 ; free virtual = 47783 INFO: [Project 1-571] Translating synthesized netlist Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 21352 ; free virtual = 47655 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 13 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1424.938 ; gain = 342.047 ; free physical = 21210 ; free virtual = 47513 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Loading data files... INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1481.742 ; gain = 0.000 ; free physical = 21206 ; free virtual = 47509 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1481.742 ; gain = 0.000 ; free physical = 21204 ; free virtual = 47506 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 20951 ; free virtual = 47253 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: eeeca7b0 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1488.969 ; gain = 0.000 ; free physical = 20943 ; free virtual = 47246 Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27007 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1424.934 ; gain = 342.047 ; free physical = 20574 ; free virtual = 46877 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. Loading site data... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.199 ; gain = 0.000 ; free physical = 20228 ; free virtual = 46531 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 20222 ; free virtual = 46524 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14eeb77a5 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1488.965 ; gain = 0.000 ; free physical = 20219 ; free virtual = 46521 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 20200 ; free virtual = 46503 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 20187 ; free virtual = 46490 Phase 1.4 Constrain Clocks/Macros Loading route data... Processing options... Creating bitmap... Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 20178 ; free virtual = 46480 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 20172 ; free virtual = 46474 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 20152 ; free virtual = 46455 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.242 ; gain = 514.531 ; free physical = 20147 ; free virtual = 46449 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.242 ; gain = 580.562 ; free physical = 20147 ; free virtual = 46449 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/top.v:2] Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading site data... Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 19878 ; free virtual = 46183 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 19788 ; free virtual = 46092 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 19787 ; free virtual = 46091 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing bitstream ./design.bit... Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 27110 Loading site data... Creating bitstream... Loading route data... Processing options... Creating bitmap... Creating bitstream... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 19690 ; free virtual = 45999 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:59:23 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2453.871 ; gain = 342.105 ; free physical = 19699 ; free virtual = 46007 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:59:23 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_007 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 20453 ; free virtual = 46761 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2] Writing bitstream ./design.bit... INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 20674 ; free virtual = 46990 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:59:29 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2463.418 ; gain = 335.176 ; free physical = 20681 ; free virtual = 46998 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:59:29 2019... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1342.102 ; gain = 246.184 ; free physical = 20730 ; free virtual = 47047 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.230 ; gain = 0.000 ; free physical = 20785 ; free virtual = 47102 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_007 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 511.531 ; free physical = 21553 ; free virtual = 47870 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 511.531 ; free physical = 21520 ; free virtual = 47837 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 511.531 ; free physical = 21492 ; free virtual = 47809 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 511.531 ; free physical = 21461 ; free virtual = 47778 Phase 2 Final Placement Cleanup Creating bitstream... Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 511.531 ; free physical = 21434 ; free virtual = 47751 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1993.273 ; gain = 511.531 ; free physical = 21410 ; free virtual = 47726 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.273 ; gain = 576.562 ; free physical = 21406 ; free virtual = 47723 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1908.457 ; gain = 0.000 ; free physical = 21381 ; free virtual = 47698 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 21381 ; free virtual = 47697 --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:59:31 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2461.859 ; gain = 340.105 ; free physical = 21396 ; free virtual = 47712 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:59:31 2019... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 21401 ; free virtual = 47717 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1b1503975 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 22357 ; free virtual = 48674 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 248a29f5b Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 22353 ; free virtual = 48670 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 248a29f5b Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 22352 ; free virtual = 48670 Phase 1 Placer Initialization | Checksum: 248a29f5b Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.500 ; gain = 507.531 ; free physical = 22351 ; free virtual = 48669 Phase 2 Global Placement touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_008 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 22220 ; free virtual = 48538 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 22214 ; free virtual = 48531 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:115] --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 22238 ; free virtual = 48556 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 22235 ; free virtual = 48552 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 22231 ; free virtual = 48548 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 22228 ; free virtual = 48546 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 22227 ; free virtual = 48545 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 22225 ; free virtual = 48543 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.086 ; gain = 254.160 ; free physical = 22227 ; free virtual = 48544 Writing bitstream ./design.bit... INFO: [Project 1-571] Translating synthesized netlist WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1908.453 ; gain = 0.000 ; free physical = 22257 ; free virtual = 48579 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2 Global Placement | Checksum: 2408ba81e Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22254 ; free virtual = 48575 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 2408ba81e Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22248 ; free virtual = 48570 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2559e6f74 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22248 ; free virtual = 48569 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 22f794d3f Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22249 ; free virtual = 48571 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1f92dada4 Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22249 ; free virtual = 48570 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 143725fd8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22243 ; free virtual = 48565 Phase 3.6 Re-assign LUT pins INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Phase 3.6 Re-assign LUT pins | Checksum: 143725fd8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22243 ; free virtual = 48564 WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 143725fd8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22243 ; free virtual = 48564 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 104554cdc Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 22243 ; free virtual = 48564 Phase 1.3 Build Placer Netlist Model Phase 3 Detail Placement | Checksum: 143725fd8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22243 ; free virtual = 48564 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 1.3 Build Placer Netlist Model | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 22242 ; free virtual = 48564 Phase 1.4 Constrain Clocks/Macros Phase 4.1 Post Commit Optimization | Checksum: 143725fd8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22242 ; free virtual = 48564 Phase 1.4 Constrain Clocks/Macros | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 22242 ; free virtual = 48564 Phase 4.2 Post Placement Cleanup Phase 1 Placer Initialization | Checksum: 19ba7b2c2 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.496 ; gain = 507.531 ; free physical = 22242 ; free virtual = 48564 Phase 2 Global Placement Phase 4.2 Post Placement Cleanup | Checksum: 143725fd8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22242 ; free virtual = 48564 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 143725fd8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22241 ; free virtual = 48562 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 143725fd8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22240 ; free virtual = 48562 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 143725fd8 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22240 ; free virtual = 48562 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:16] Ending Placer Task | Checksum: fb45469f Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.547 ; gain = 603.578 ; free physical = 22254 ; free virtual = 48576 23 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.547 ; gain = 667.609 ; free physical = 22254 ; free virtual = 48576 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 22193 ; free virtual = 48515 --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 22152 ; free virtual = 48474 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 22151 ; free virtual = 48474 --------------------------------------------------------------------------------- INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 16a59d95 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_005/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 03:59:37 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:31 . Memory (MB): peak = 2470.266 ; gain = 338.105 ; free physical = 22121 ; free virtual = 48443 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 03:59:37 2019... INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/top.v:2] Phase 2 Global Placement | Checksum: 19390bb85 Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 22187 ; free virtual = 48509 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 19390bb85 Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 22194 ; free virtual = 48516 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 22760be29 Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 22220 ; free virtual = 48542 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 2013b9bf4 Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 23132 ; free virtual = 49457 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1caeffc59 Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 23130 ; free virtual = 49456 Phase 3.5 Small Shape Detail Placement Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds Phase 3.5 Small Shape Detail Placement | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 23029 ; free virtual = 49367 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 23027 ; free virtual = 49365 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 23025 ; free virtual = 49364 WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 3 Detail Placement | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 23024 ; free virtual = 49363 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 23020 ; free virtual = 49361 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 23016 ; free virtual = 49358 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 23014 ; free virtual = 49357 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 23014 ; free virtual = 49357 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 21932cca2 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 23013 ; free virtual = 49356 Ending Placer Task | Checksum: 1d105b369 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2092.543 ; gain = 603.578 ; free physical = 23023 ; free virtual = 49367 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2092.543 ; gain = 667.609 ; free physical = 23023 ; free virtual = 49366 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_005/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_009 INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 22938 ; free virtual = 49263 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1266.969 ; gain = 171.352 ; free physical = 22952 ; free virtual = 49277 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: ec660a5f ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 22897 ; free virtual = 49222 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 22897 ; free virtual = 49222 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 1370b43a3 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.957 ; gain = 43.668 ; free physical = 22461 ; free virtual = 48787 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1370b43a3 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 22427 ; free virtual = 48752 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1370b43a3 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 22426 ; free virtual = 48752 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 1338.066 ; gain = 242.152 ; free physical = 22446 ; free virtual = 48772 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 157ee683c Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2087.250 ; gain = 60.961 ; free physical = 22429 ; free virtual = 48755 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 22410 ; free virtual = 48736 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 22393 ; free virtual = 48718 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 3 Initial Routing | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 22392 ; free virtual = 48718 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 4.1 Global Iteration 0 | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 22381 ; free virtual = 48706 Phase 4 Rip-up And Reroute | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 22378 ; free virtual = 48704 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 22377 ; free virtual = 48702 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 22372 ; free virtual = 48697 Phase 6 Post Hold Fix | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 22366 ; free virtual = 48691 Phase 7 Route finalize INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 22352 ; free virtual = 48677 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 157ee683c Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 22345 ; free virtual = 48671 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 157ee683c Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2092.250 ; gain = 65.961 ; free physical = 22279 ; free virtual = 48604 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2092.250 ; gain = 65.961 ; free physical = 22305 ; free virtual = 48631 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2131.039 ; gain = 136.766 ; free physical = 22315 ; free virtual = 48640 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 22331 ; free virtual = 48656 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes Writing placer database... INFO: Helper process launched with PID 28909 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.90 ; elapsed = 00:00:00.61 . Memory (MB): peak = 2131.039 ; gain = 0.000 ; free physical = 22279 ; free virtual = 48607 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 22241 ; free virtual = 48567 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 22237 ; free virtual = 48563 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 22215 ; free virtual = 48541 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 22212 ; free virtual = 48538 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 22208 ; free virtual = 48534 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 22205 ; free virtual = 48531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 22203 ; free virtual = 48529 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 22200 ; free virtual = 48526 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 22195 ; free virtual = 48522 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 22140 ; free virtual = 48467 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1342.098 ; gain = 246.184 ; free physical = 22110 ; free virtual = 48436 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 22073 ; free virtual = 48399 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 28971 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 21883 ; free virtual = 48209 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 21834 ; free virtual = 48160 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 21797 ; free virtual = 48123 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 21799 ; free virtual = 48125 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 21813 ; free virtual = 48140 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 21817 ; free virtual = 48143 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 21815 ; free virtual = 48142 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.074 ; gain = 254.160 ; free physical = 21814 ; free virtual = 48140 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.082 ; gain = 254.160 ; free physical = 21816 ; free virtual = 48142 Loading data files... INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29008 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 21719 ; free virtual = 48045 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:04 . Memory (MB): peak = 1476.828 ; gain = 393.938 ; free physical = 21736 ; free virtual = 48063 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2062.926 ; gain = 44.668 ; free physical = 21709 ; free virtual = 48036 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.914 ; gain = 50.656 ; free physical = 21672 ; free virtual = 47999 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.914 ; gain = 50.656 ; free physical = 21664 ; free virtual = 47990 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2077.969 ; gain = 59.711 ; free physical = 21570 ; free virtual = 47896 Phase 3 Initial Routing INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:1575] Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 21560 ; free virtual = 47886 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/top.v:2] Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 21565 ; free virtual = 47891 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 21566 ; free virtual = 47893 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 21568 ; free virtual = 47894 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 21569 ; free virtual = 47895 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 21570 ; free virtual = 47897 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 21596 ; free virtual = 47922 --------------------------------------------------------------------------------- Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 21597 ; free virtual = 47924 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 21599 ; free virtual = 47926 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 21608 ; free virtual = 47935 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 21609 ; free virtual = 47936 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 21613 ; free virtual = 47940 --------------------------------------------------------------------------------- INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 21646 ; free virtual = 47973 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2121.758 ; gain = 135.516 ; free physical = 21647 ; free virtual = 47973 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 21661 ; free virtual = 47988 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2121.758 ; gain = 0.000 ; free physical = 21657 ; free virtual = 47986 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Placer Initialization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1556.859 ; gain = 0.000 ; free physical = 21602 ; free virtual = 47929 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 21606 ; free virtual = 47933 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1556.859 ; gain = 0.000 ; free physical = 21589 ; free virtual = 47916 INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1545.953 ; gain = 0.000 ; free physical = 21526 ; free virtual = 47853 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.51 . Memory (MB): peak = 1545.953 ; gain = 0.000 ; free physical = 21498 ; free virtual = 47825 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 21393 ; free virtual = 47720 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 29109 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 21373 ; free virtual = 47700 --------------------------------------------------------------------------------- Loading site data... Loading route data... Processing options... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Creating bitmap... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:22] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 21042 ; free virtual = 47369 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:15] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:652] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 21055 ; free virtual = 47382 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:652] Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:687] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 21054 ; free virtual = 47381 --------------------------------------------------------------------------------- Loading data files... INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 21051 ; free virtual = 47378 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 21073 ; free virtual = 47400 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 21044 ; free virtual = 47373 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 21043 ; free virtual = 47371 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 21028 ; free virtual = 47356 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 20782 ; free virtual = 47110 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.691 ; gain = 207.242 ; free physical = 20775 ; free virtual = 47102 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20767 ; free virtual = 47094 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20717 ; free virtual = 47045 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20717 ; free virtual = 47045 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20715 ; free virtual = 47043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20715 ; free virtual = 47043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20715 ; free virtual = 47043 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20715 ; free virtual = 47042 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20714 ; free virtual = 47042 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20713 ; free virtual = 47041 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.676 ; gain = 215.219 ; free physical = 20714 ; free virtual = 47042 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 20478 ; free virtual = 46805 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: cea32407 Time (s): cpu = 00:00:40 ; elapsed = 00:00:38 . Memory (MB): peak = 2067.957 ; gain = 42.668 ; free physical = 20463 ; free virtual = 46790 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: cea32407 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2074.945 ; gain = 49.656 ; free physical = 20429 ; free virtual = 46757 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: cea32407 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2074.945 ; gain = 49.656 ; free physical = 20429 ; free virtual = 46757 Creating bitstream... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1bf4d4050 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2087.250 ; gain = 61.961 ; free physical = 20372 ; free virtual = 46700 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 3 Initial Routing | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 20337 ; free virtual = 46664 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 20326 ; free virtual = 46653 Phase 4 Rip-up And Reroute | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 20324 ; free virtual = 46652 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 20322 ; free virtual = 46650 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 20321 ; free virtual = 46649 Phase 6 Post Hold Fix | Checksum: 1bf4d4050 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 20319 ; free virtual = 46647 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 7 Route finalize | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2088.250 ; gain = 62.961 ; free physical = 20295 ; free virtual = 46622 Phase 8 Verifying routed nets Verification completed successfully --------------------------------------------------------------------------------- Phase 8 Verifying routed nets | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2091.250 ; gain = 65.961 ; free physical = 20293 ; free virtual = 46620 Phase 9 Depositing Routes Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 20292 ; free virtual = 46620 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.922 ; gain = 210.484 ; free physical = 20279 ; free virtual = 46607 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 1bf4d4050 Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2091.250 ; gain = 65.961 ; free physical = 20277 ; free virtual = 46604 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2091.250 ; gain = 65.961 ; free physical = 20311 ; free virtual = 46639 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:41 . Memory (MB): peak = 2130.039 ; gain = 136.766 ; free physical = 20312 ; free virtual = 46639 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 20297 ; free virtual = 46625 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:225] Writing placer database... WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/top.v:2] Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2130.039 ; gain = 0.000 ; free physical = 20307 ; free virtual = 46638 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20306 ; free virtual = 46642 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20308 ; free virtual = 46640 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20307 ; free virtual = 46639 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20321 ; free virtual = 46653 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1397.691 ; gain = 314.797 ; free physical = 20334 ; free virtual = 46664 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 20331 ; free virtual = 46659 --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 20313 ; free virtual = 46642 INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20272 ; free virtual = 46600 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 20264 ; free virtual = 46593 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 20259 ; free virtual = 46587 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 20252 ; free virtual = 46581 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 20251 ; free virtual = 46579 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 20246 ; free virtual = 46575 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 20244 ; free virtual = 46572 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 20241 ; free virtual = 46570 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.898 ; gain = 218.461 ; free physical = 20234 ; free virtual = 46563 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20234 ; free virtual = 46563 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks Loading site data... INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20480 ; free virtual = 46812 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20477 ; free virtual = 46810 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20472 ; free virtual = 46804 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20471 ; free virtual = 46804 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20469 ; free virtual = 46802 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20468 ; free virtual = 46801 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20469 ; free virtual = 46802 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20468 ; free virtual = 46801 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 20470 ; free virtual = 46802 Starting Placer Task INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 20453 ; free virtual = 46786 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1462.723 ; gain = 0.000 ; free physical = 20448 ; free virtual = 46780 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading route data... Processing options... Creating bitmap... INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 1476.824 ; gain = 393.938 ; free physical = 20148 ; free virtual = 46481 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:00:17 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:29 . Memory (MB): peak = 2469.145 ; gain = 338.105 ; free physical = 19973 ; free virtual = 46305 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:00:17 2019... Phase 1 Build RT Design | Checksum: 19d034a6e Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 19974 ; free virtual = 46306 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 19d034a6e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 20013 ; free virtual = 46346 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 19d034a6e Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2092.547 ; gain = 0.000 ; free physical = 20022 ; free virtual = 46355 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Bitstream size: 4243411 bytes Config size: 1060815 words INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Number of configuration frames: 9996 DONE Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1964.348 ; gain = 0.000 ; free physical = 20848 ; free virtual = 47181 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 174587064 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 20701 ; free virtual = 47034 Phase 3 Initial Routing touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_010 Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 20697 ; free virtual = 47030 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 20697 ; free virtual = 47031 Phase 4 Rip-up And Reroute | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 20703 ; free virtual = 47036 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 20706 ; free virtual = 47039 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 20707 ; free virtual = 47041 Phase 6 Post Hold Fix | Checksum: 708f6dc3 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 20707 ; free virtual = 47041 Phase 7 Route finalize Starting Placer Task 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.922 ; gain = 324.039 ; free physical = 20722 ; free virtual = 47056 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 7 Route finalize | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 20688 ; free virtual = 47022 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 20684 ; free virtual = 47017 Phase 9 Depositing Routes Phase 1 Placer Initialization Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.1 Placer Initialization Netlist Sorting Phase 9 Depositing Routes | Checksum: 708f6dc3 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 20653 ; free virtual = 46986 Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1559.855 ; gain = 0.000 ; free physical = 20689 ; free virtual = 47023 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2103.230 ; gain = 10.684 ; free physical = 20690 ; free virtual = 47023 Routing Is Done. 30 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2142.020 ; gain = 49.473 ; free physical = 20688 ; free virtual = 47022 Writing placer database... Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.48 . Memory (MB): peak = 1559.855 ; gain = 0.000 ; free physical = 20614 ; free virtual = 46948 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2142.020 ; gain = 0.000 ; free physical = 20515 ; free virtual = 46852 Phase 1 Build RT Design | Checksum: 1c3aa3009 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 20478 ; free virtual = 46814 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1c3aa3009 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 20433 ; free virtual = 46770 Phase 2.2 Pre Route Cleanup INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2.2 Pre Route Cleanup | Checksum: 1c3aa3009 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2092.543 ; gain = 0.000 ; free physical = 20434 ; free virtual = 46768 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 20334 ; free virtual = 46669 Phase 1.3 Build Placer Netlist Model 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 20343 ; free virtual = 46677 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Placer Task INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.953 ; gain = 0.000 ; free physical = 20358 ; free virtual = 46693 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1471.953 ; gain = 0.000 ; free physical = 20363 ; free virtual = 46698 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 171fe028c Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.227 ; gain = 7.684 ; free physical = 20359 ; free virtual = 46693 Phase 3 Initial Routing Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.227 ; gain = 7.684 ; free physical = 20357 ; free virtual = 46694 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 20356 ; free virtual = 46693 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.227 ; gain = 7.684 ; free physical = 20351 ; free virtual = 46690 Phase 4 Rip-up And Reroute | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.227 ; gain = 7.684 ; free physical = 20352 ; free virtual = 46687 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.227 ; gain = 7.684 ; free physical = 20350 ; free virtual = 46685 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 6.1 Hold Fix Iter | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.227 ; gain = 7.684 ; free physical = 20343 ; free virtual = 46677 Phase 6 Post Hold Fix | Checksum: 6d35d7ab Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.227 ; gain = 7.684 ; free physical = 20339 ; free virtual = 46674 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device %, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.227 ; gain = 7.684 ; free physical = 20338 ; free virtual = 46672 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.227 ; gain = 7.684 ; free physical = 20336 ; free virtual = 46670 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6d35d7ab Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.227 ; gain = 7.684 ; free physical = 20325 ; free virtual = 46659 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2100.227 ; gain = 7.684 ; free physical = 20359 ; free virtual = 46694 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:42 . Memory (MB): peak = 2139.016 ; gain = 46.473 ; free physical = 20360 ; free virtual = 46694 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 20352 ; free virtual = 46687 --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Writing XDEF routing logical nets. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Writing XDEF routing special nets. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 20352 ; free virtual = 46688 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2139.016 ; gain = 0.000 ; free physical = 20350 ; free virtual = 46687 Starting Placer Task --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20337 ; free virtual = 46674 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 20336 ; free virtual = 46673 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 20333 ; free virtual = 46670 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20291 ; free virtual = 46626 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20289 ; free virtual = 46624 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20283 ; free virtual = 46618 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20282 ; free virtual = 46617 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20280 ; free virtual = 46615 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 --------------------------------------------------------------------------------- Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 20279 ; free virtual = 46614 Phase 1.3 Build Placer Netlist Model Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20278 ; free virtual = 46613 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20275 ; free virtual = 46610 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. INFO: [DRC 23-27] Running DRC with 8 threads Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 20268 ; free virtual = 46603 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 20268 ; free virtual = 46603 INFO: [Project 1-571] Translating synthesized netlist Writing bitstream ./design.bit... INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 20387 ; free virtual = 46726 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 20388 ; free virtual = 46727 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 20346 ; free virtual = 46685 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 20375 ; free virtual = 46714 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Loading data files... Time (s): cpu = 00:00:24 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.391 ; gain = 495.531 ; free physical = 20357 ; free virtual = 46696 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.391 ; gain = 575.562 ; free physical = 20350 ; free virtual = 46689 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 20274 ; free virtual = 46613 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 20199 ; free virtual = 46539 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 20165 ; free virtual = 46504 Phase 2 Global Placement INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:00:27 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:29 . Memory (MB): peak = 2459.863 ; gain = 338.105 ; free physical = 20095 ; free virtual = 46435 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:00:27 2019... Loading data files... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_007 Phase 1 Build RT Design WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Loading site data... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 20871 ; free virtual = 47210 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Loading route data... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Processing options... Creating bitmap... Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:26 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20783 ; free virtual = 47123 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20756 ; free virtual = 47096 Phase 3.2 Commit Most Macros & LUTRAMs report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20827 ; free virtual = 47167 Starting Placer Task Phase 3.3 Area Swap Optimization INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 20825 ; free virtual = 47165 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1471.961 ; gain = 0.000 ; free physical = 20801 ; free virtual = 47140 Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20799 ; free virtual = 47139 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20791 ; free virtual = 47130 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20627 ; free virtual = 46967 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20536 ; free virtual = 46876 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20562 ; free virtual = 46902 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20522 ; free virtual = 46861 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20406 ; free virtual = 46746 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20339 ; free virtual = 46679 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20291 ; free virtual = 46631 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20264 ; free virtual = 46603 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.211 ; gain = 0.000 ; free physical = 20252 ; free virtual = 46592 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20249 ; free virtual = 46589 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 20259 ; free virtual = 46599 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 20259 ; free virtual = 46599 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 20053 ; free virtual = 46393 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 20052 ; free virtual = 46392 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 20052 ; free virtual = 46392 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 20052 ; free virtual = 46392 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 20053 ; free virtual = 46393 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.254 ; gain = 469.531 ; free physical = 20054 ; free virtual = 46394 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1932.254 ; gain = 534.562 ; free physical = 20055 ; free virtual = 46395 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading route data... Processing options... Creating bitmap... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading site data... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.441 ; gain = 0.000 ; free physical = 19087 ; free virtual = 45431 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 19192 ; free virtual = 45535 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 19152 ; free virtual = 45496 Phase 1.4 Constrain Clocks/Macros INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 19153 ; free virtual = 45496 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 19148 ; free virtual = 45492 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 19141 ; free virtual = 45485 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.484 ; gain = 518.531 ; free physical = 19117 ; free virtual = 45461 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1990.484 ; gain = 583.562 ; free physical = 19115 ; free virtual = 45459 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.344 ; gain = 0.000 ; free physical = 19113 ; free virtual = 45457 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Creating bitstream... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30331 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 19085 ; free virtual = 45429 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 19051 ; free virtual = 45395 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 19040 ; free virtual = 45383 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 19025 ; free virtual = 45369 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 19026 ; free virtual = 45370 Phase 2 Final Placement Cleanup INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 19004 ; free virtual = 45348 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 19008 ; free virtual = 45352 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 19008 ; free virtual = 45352 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.387 ; gain = 492.531 ; free physical = 18901 ; free virtual = 45245 Phase 1.3 Build Placer Netlist Model Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:00:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:41 ; elapsed = 00:00:34 . Memory (MB): peak = 2470.145 ; gain = 340.105 ; free physical = 18903 ; free virtual = 45247 Writing bitstream ./design.bit... INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:00:46 2019... Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:00:50 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 40 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:36 ; elapsed = 00:00:31 . Memory (MB): peak = 2475.125 ; gain = 333.105 ; free physical = 20349 ; free virtual = 46703 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:00:50 2019... Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.387 ; gain = 492.531 ; free physical = 20353 ; free virtual = 46707 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.387 ; gain = 492.531 ; free physical = 20420 ; free virtual = 46773 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.387 ; gain = 492.531 ; free physical = 21285 ; free virtual = 47638 Phase 2 Final Placement Cleanup Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.387 ; gain = 492.531 ; free physical = 21300 ; free virtual = 47654 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:32 . Memory (MB): peak = 2052.387 ; gain = 492.531 ; free physical = 21289 ; free virtual = 47644 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:35 . Memory (MB): peak = 2052.387 ; gain = 575.562 ; free physical = 21276 ; free virtual = 47630 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:00:52 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2474.121 ; gain = 335.105 ; free physical = 21021 ; free virtual = 47375 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:00:52 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 21936 ; free virtual = 48291 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 21910 ; free virtual = 48265 touch build/specimen_011/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 2 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_012 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 21813 ; free virtual = 48168 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 21794 ; free virtual = 48149 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 21774 ; free virtual = 48130 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 21767 ; free virtual = 48122 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 21757 ; free virtual = 48113 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 519.531 ; free physical = 21755 ; free virtual = 48111 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 21755 ; free virtual = 48111 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30671 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:456] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 21726 ; free virtual = 48082 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 21715 ; free virtual = 48071 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 21713 ; free virtual = 48070 --------------------------------------------------------------------------------- Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 21683 ; free virtual = 48039 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 21298 ; free virtual = 47654 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 21209 ; free virtual = 47566 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 21202 ; free virtual = 47558 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 21193 ; free virtual = 47549 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:28] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 21208 ; free virtual = 47565 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 21169 ; free virtual = 47526 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 21169 ; free virtual = 47526 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 21163 ; free virtual = 47520 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 21162 ; free virtual = 47518 --------------------------------------------------------------------------------- No constraint files found. INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 21198 ; free virtual = 47554 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 21204 ; free virtual = 47560 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 21204 ; free virtual = 47560 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 21203 ; free virtual = 47560 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 21203 ; free virtual = 47559 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 21203 ; free virtual = 47559 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 21202 ; free virtual = 47558 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.918 ; gain = 218.461 ; free physical = 21204 ; free virtual = 47560 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30763 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1406.934 ; gain = 324.039 ; free physical = 20807 ; free virtual = 47164 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 1ca097e33 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2133.074 ; gain = 48.668 ; free physical = 20733 ; free virtual = 47090 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1ca097e33 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2143.062 ; gain = 58.656 ; free physical = 20683 ; free virtual = 47039 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1ca097e33 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2143.062 ; gain = 58.656 ; free physical = 20683 ; free virtual = 47039 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1472.965 ; gain = 0.000 ; free physical = 20669 ; free virtual = 47025 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1472.965 ; gain = 0.000 ; free physical = 20667 ; free virtual = 47024 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 30822 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 130bdaadd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 20634 ; free virtual = 46990 Phase 3 Initial Routing ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 130bdaadd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 20580 ; free virtual = 46938 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 4.1 Global Iteration 0 | Checksum: 130bdaadd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 20575 ; free virtual = 46931 Phase 4 Rip-up And Reroute | Checksum: 130bdaadd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 20596 ; free virtual = 46952 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 130bdaadd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 20592 ; free virtual = 46949 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 130bdaadd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 20592 ; free virtual = 46948 Phase 6 Post Hold Fix | Checksum: 130bdaadd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 20591 ; free virtual = 46948 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 130bdaadd Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 20582 ; free virtual = 46939 Phase 8 Verifying routed nets Verification completed successfully No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 8 Verifying routed nets | Checksum: 130bdaadd Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 20579 ; free virtual = 46935 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 20580 ; free virtual = 46937 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 20565 ; free virtual = 46921 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 20566 ; free virtual = 46923 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 130bdaadd Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 20562 ; free virtual = 46918 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.492 ; gain = 95.086 ; free physical = 20605 ; free virtual = 46962 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:48 . Memory (MB): peak = 2218.281 ; gain = 165.891 ; free physical = 20605 ; free virtual = 46961 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing placer database... INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 20568 ; free virtual = 46930 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 20565 ; free virtual = 46927 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 20563 ; free virtual = 46926 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 20563 ; free virtual = 46926 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 20563 ; free virtual = 46926 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 20569 ; free virtual = 46932 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 20569 ; free virtual = 46932 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. INFO: Launching helper process for spawning children vivado processes Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 20569 ; free virtual = 46932 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 20570 ; free virtual = 46932 INFO: Helper process launched with PID 30867 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2218.281 ; gain = 0.000 ; free physical = 20459 ; free virtual = 46844 Phase 1 Build RT Design | Checksum: 154656e26 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2056.938 ; gain = 92.668 ; free physical = 20459 ; free virtual = 46843 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 154656e26 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2061.926 ; gain = 97.656 ; free physical = 20425 ; free virtual = 46810 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 154656e26 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2061.926 ; gain = 97.656 ; free physical = 20425 ; free virtual = 46810 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 790be677 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 20415 ; free virtual = 46801 Phase 3 Initial Routing --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 20407 ; free virtual = 46793 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 790be677 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 20400 ; free virtual = 46788 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 20398 ; free virtual = 46786 Phase 4 Rip-up And Reroute | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 20398 ; free virtual = 46786 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 20398 ; free virtual = 46786 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 20398 ; free virtual = 46786 Phase 6 Post Hold Fix | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 20399 ; free virtual = 46786 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2129.430 ; gain = 30.227 ; free physical = 20399 ; free virtual = 46786 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 7 Route finalize | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2068.980 ; gain = 104.711 ; free physical = 20393 ; free virtual = 46753 Phase 8 Verifying routed nets Phase 2.1 Fix Topology Constraints Verification completed successfully Phase 8 Verifying routed nets | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 20391 ; free virtual = 46751 Phase 9 Depositing Routes Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2136.418 ; gain = 37.215 ; free physical = 20391 ; free virtual = 46751 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2136.418 ; gain = 37.215 ; free physical = 20392 ; free virtual = 46752 Phase 9 Depositing Routes | Checksum: 790be677 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 20392 ; free virtual = 46752 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2071.980 ; gain = 107.711 ; free physical = 20420 ; free virtual = 46780 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2110.770 ; gain = 178.516 ; free physical = 20420 ; free virtual = 46780 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2110.770 ; gain = 0.000 ; free physical = 20398 ; free virtual = 46759 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.473 ; gain = 56.270 ; free physical = 20307 ; free virtual = 46667 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.473 ; gain = 56.270 ; free physical = 20314 ; free virtual = 46674 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.473 ; gain = 56.270 ; free physical = 20300 ; free virtual = 46660 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.473 ; gain = 56.270 ; free physical = 20300 ; free virtual = 46660 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.473 ; gain = 56.270 ; free physical = 20300 ; free virtual = 46660 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.473 ; gain = 56.270 ; free physical = 20300 ; free virtual = 46660 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.473 ; gain = 56.270 ; free physical = 20300 ; free virtual = 46660 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.473 ; gain = 56.270 ; free physical = 20333 ; free virtual = 46693 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.473 ; gain = 56.270 ; free physical = 20331 ; free virtual = 46691 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.473 ; gain = 56.270 ; free physical = 20328 ; free virtual = 46688 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2155.473 ; gain = 56.270 ; free physical = 20363 ; free virtual = 46723 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:45 . Memory (MB): peak = 2194.262 ; gain = 95.059 ; free physical = 20361 ; free virtual = 46721 Running DRC as a precondition to command write_bitstream Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing placer database... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 20285 ; free virtual = 46663 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 20313 ; free virtual = 46684 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 20267 ; free virtual = 46639 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 20265 ; free virtual = 46637 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 20265 ; free virtual = 46637 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 20262 ; free virtual = 46638 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1470.711 ; gain = 0.000 ; free physical = 20192 ; free virtual = 46570 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1470.711 ; gain = 0.000 ; free physical = 20184 ; free virtual = 46562 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2194.262 ; gain = 0.000 ; free physical = 20089 ; free virtual = 46472 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:496] INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2067.168 ; gain = 44.668 ; free physical = 20058 ; free virtual = 46443 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2073.156 ; gain = 50.656 ; free physical = 20034 ; free virtual = 46395 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2073.156 ; gain = 50.656 ; free physical = 20031 ; free virtual = 46392 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 19968 ; free virtual = 46329 --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/top.v:2] Loading data files... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2083.461 ; gain = 60.961 ; free physical = 19956 ; free virtual = 46318 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 20020 ; free virtual = 46382 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 20019 ; free virtual = 46382 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 20013 ; free virtual = 46376 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 20013 ; free virtual = 46376 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 20016 ; free virtual = 46379 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 20023 ; free virtual = 46386 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 20025 ; free virtual = 46388 Running DRC as a precondition to command write_bitstream Phase 7 Route finalize Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2085.461 ; gain = 62.961 ; free physical = 20005 ; free virtual = 46376 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2088.461 ; gain = 65.961 ; free physical = 19999 ; free virtual = 46370 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 19990 ; free virtual = 46352 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:13 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 19989 ; free virtual = 46351 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2088.461 ; gain = 65.961 ; free physical = 19984 ; free virtual = 46346 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2088.461 ; gain = 65.961 ; free physical = 20018 ; free virtual = 46381 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2127.250 ; gain = 136.766 ; free physical = 20014 ; free virtual = 46377 INFO: [Device 21-403] Loading part xc7z020clg400-1 Writing placer database... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.61 . Memory (MB): peak = 2127.250 ; gain = 0.000 ; free physical = 19853 ; free virtual = 46219 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 19841 ; free virtual = 46207 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:27] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 1 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:111] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:167] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:251] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:279] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:391] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:419] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:447] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:503] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:559] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:587] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:615] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:671] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:699] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:727] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:755] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:839] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:895] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:923] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:951] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1007] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1035] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1063] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1091] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1119] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1231] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1287] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1371] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1399] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1511] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1539] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1623] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1651] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1679] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1707] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1735] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1791] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1819] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1847] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1875] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1959] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:1987] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2015] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2043] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2071] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2743] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2771] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2799] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.176 ; gain = 43.668 ; free physical = 19740 ; free virtual = 46103 WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:16] Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 19669 ; free virtual = 46032 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 19672 ; free virtual = 46035 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 19782 ; free virtual = 46145 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 19776 ; free virtual = 46139 Phase 3 Initial Routing Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 19776 ; free virtual = 46139 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 19775 ; free virtual = 46138 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 19749 ; free virtual = 46112 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 19742 ; free virtual = 46106 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 19738 ; free virtual = 46102 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 19736 ; free virtual = 46100 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1210.961 ; gain = 115.508 ; free physical = 19725 ; free virtual = 46089 --------------------------------------------------------------------------------- Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 19725 ; free virtual = 46088 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 19724 ; free virtual = 46088 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2085.469 ; gain = 61.961 ; free physical = 19687 ; free virtual = 46050 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 19684 ; free virtual = 46048 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 19669 ; free virtual = 46032 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.469 ; gain = 64.961 ; free physical = 19705 ; free virtual = 46068 Routing Is Done. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:43 . Memory (MB): peak = 2127.258 ; gain = 135.766 ; free physical = 19704 ; free virtual = 46068 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2127.258 ; gain = 0.000 ; free physical = 19526 ; free virtual = 45892 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 19245 ; free virtual = 45609 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 19003 ; free virtual = 45367 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Loading data files... --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18969 ; free virtual = 45333 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Timing 38-35] Done setting XDC timing constraints. Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.453 ; gain = 0.000 ; free physical = 18857 ; free virtual = 45221 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18868 ; free virtual = 45232 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18867 ; free virtual = 45231 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18865 ; free virtual = 45230 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18865 ; free virtual = 45229 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18864 ; free virtual = 45228 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18864 ; free virtual = 45228 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18863 ; free virtual = 45227 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 18860 ; free virtual = 45224 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.688 ; gain = 225.230 ; free physical = 18860 ; free virtual = 45224 INFO: [Project 1-571] Translating synthesized netlist Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 18784 ; free virtual = 45148 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 18755 ; free virtual = 45119 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 18765 ; free virtual = 45129 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 18767 ; free virtual = 45131 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 18758 ; free virtual = 45122 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1991.496 ; gain = 518.531 ; free physical = 18734 ; free virtual = 45098 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 1991.496 ; gain = 584.562 ; free physical = 18732 ; free virtual = 45096 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 14c2f3401 Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2134.070 ; gain = 49.668 ; free physical = 18572 ; free virtual = 44936 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 14c2f3401 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2143.059 ; gain = 58.656 ; free physical = 18483 ; free virtual = 44847 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 14c2f3401 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2143.059 ; gain = 58.656 ; free physical = 18482 ; free virtual = 44846 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 18317 ; free virtual = 44681 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Loading data files... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 15a0a7f4a Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 2179.363 ; gain = 94.961 ; free physical = 18281 ; free virtual = 44645 Phase 3 Initial Routing Loading site data... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 18279 ; free virtual = 44643 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18272 ; free virtual = 44636 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2179.363 ; gain = 94.961 ; free physical = 18229 ; free virtual = 44598 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2179.363 ; gain = 94.961 ; free physical = 18227 ; free virtual = 44592 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Phase 4 Rip-up And Reroute | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2179.363 ; gain = 94.961 ; free physical = 18220 ; free virtual = 44585 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2179.363 ; gain = 94.961 ; free physical = 18219 ; free virtual = 44583 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2179.363 ; gain = 94.961 ; free physical = 18211 ; free virtual = 44575 Phase 6 Post Hold Fix | Checksum: 15a0a7f4a Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2179.363 ; gain = 94.961 ; free physical = 18200 ; free virtual = 44564 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 7 Route finalize | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:41 . Memory (MB): peak = 2179.363 ; gain = 94.961 ; free physical = 18177 ; free virtual = 44542 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:41 . Memory (MB): peak = 2179.363 ; gain = 94.961 ; free physical = 18172 ; free virtual = 44537 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 18146 ; free virtual = 44511 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18137 ; free virtual = 44501 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2067.176 ; gain = 43.668 ; free physical = 18136 ; free virtual = 44500 Finished Renaming Generated Instances : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18136 ; free virtual = 44500 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18135 ; free virtual = 44499 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18135 ; free virtual = 44499 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18135 ; free virtual = 44499 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Phase 2 Router Initialization --------------------------------------------------------------------------------- INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Finished Renaming Generated Nets : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18134 ; free virtual = 44498 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18128 ; free virtual = 44492 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1331.926 ; gain = 236.473 ; free physical = 18122 ; free virtual = 44486 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 18113 ; free virtual = 44477 Synthesis Optimization Complete : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 18108 ; free virtual = 44472 Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 18103 ; free virtual = 44467 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2073.164 ; gain = 49.656 ; free physical = 18103 ; free virtual = 44467 Phase 9 Depositing Routes | Checksum: 15a0a7f4a Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.363 ; gain = 94.961 ; free physical = 18096 ; free virtual = 44461 INFO: [Project 1-571] Translating synthesized netlist INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2179.363 ; gain = 94.961 ; free physical = 18117 ; free virtual = 44481 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:44 . Memory (MB): peak = 2218.152 ; gain = 165.766 ; free physical = 18126 ; free virtual = 44490 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 18126 ; free virtual = 44490 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing placer database... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2084.469 ; gain = 60.961 ; free physical = 18059 ; free virtual = 44427 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 18031 ; free virtual = 44402 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 18019 ; free virtual = 44390 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 18009 ; free virtual = 44380 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 18008 ; free virtual = 44379 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 18006 ; free virtual = 44376 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2086.469 ; gain = 62.961 ; free physical = 18004 ; free virtual = 44375 Creating bitstream... Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 17981 ; free virtual = 44352 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 17977 ; free virtual = 44348 --------------------------------------------------------------------------------- Report RTL Partitions: Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 17975 ; free virtual = 44346 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2087.469 ; gain = 63.961 ; free physical = 17974 ; free virtual = 44345 Phase 8 Verifying routed nets Verification completed successfully --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 17965 ; free virtual = 44337 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 17965 ; free virtual = 44337 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 17964 ; free virtual = 44336 Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 17964 ; free virtual = 44336 Phase 9 Depositing Routes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| |2 |RAMB18E1 | 140| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 155| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 17964 ; free virtual = 44336 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 142 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.941 ; gain = 246.488 ; free physical = 17961 ; free virtual = 44334 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1341.949 ; gain = 246.488 ; free physical = 17961 ; free virtual = 44334 Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 17961 ; free virtual = 44334 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2089.469 ; gain = 65.961 ; free physical = 17998 ; free virtual = 44371 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2128.258 ; gain = 136.766 ; free physical = 17998 ; free virtual = 44371 INFO: [Project 1-571] Translating synthesized netlist Writing placer database... INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2128.258 ; gain = 0.000 ; free physical = 17919 ; free virtual = 44299 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Netlist 29-17] Analyzing 143 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Running DRC as a precondition to command write_bitstream INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 17856 ; free virtual = 44242 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2218.152 ; gain = 0.000 ; free physical = 17777 ; free virtual = 44170 Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 17938 ; free virtual = 44338 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1482.742 ; gain = 0.000 ; free physical = 17946 ; free virtual = 44346 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading site data... Loading site data... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Loading route data... Processing options... Creating bitmap... Loading route data... Processing options... Creating bitmap... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:01:43 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2449.945 ; gain = 339.176 ; free physical = 17096 ; free virtual = 43468 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:01:43 2019... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.199 ; gain = 0.000 ; free physical = 17180 ; free virtual = 43552 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 18023 ; free virtual = 44395 Phase 1.3 Build Placer Netlist Model Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 18029 ; free virtual = 44400 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 18025 ; free virtual = 44397 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 18019 ; free virtual = 44390 Phase 2 Final Placement Cleanup INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 18013 ; free virtual = 44385 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1987.242 ; gain = 516.531 ; free physical = 18018 ; free virtual = 44390 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1987.242 ; gain = 581.562 ; free physical = 18022 ; free virtual = 44394 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 18070 ; free virtual = 44442 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design 15 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:31 . Memory (MB): peak = 1424.941 ; gain = 342.047 ; free physical = 18125 ; free virtual = 44497 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Creating bitstream... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1483.742 ; gain = 0.000 ; free physical = 18004 ; free virtual = 44376 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1483.742 ; gain = 0.000 ; free physical = 18006 ; free virtual = 44378 Loading site data... Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 18047 ; free virtual = 44419 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 165c53615 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1488.973 ; gain = 0.000 ; free physical = 18045 ; free virtual = 44416 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:01:53 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:01:53 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2470.355 ; gain = 343.105 ; free physical = 18505 ; free virtual = 44889 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2533.367 ; gain = 339.105 ; free physical = 18506 ; free virtual = 44890 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:01:53 2019... INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:01:53 2019... Loading data files... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Bitstream size: 4243411 bytes DONE Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_006/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_007 touch build/specimen_007/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_008 Loading site data... Writing bitstream ./design.bit... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:01:55 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2463.434 ; gain = 336.176 ; free physical = 20254 ; free virtual = 46642 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:01:55 2019... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_009 Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_006/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:01:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:42 . Memory (MB): peak = 2608.402 ; gain = 390.121 ; free physical = 21362 ; free virtual = 47753 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:01:59 2019... Writing bitstream ./design.bit... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. touch build/specimen_006/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_008 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 22459 ; free virtual = 48857 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 22460 ; free virtual = 48862 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 22446 ; free virtual = 48848 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 22434 ; free virtual = 48836 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 22405 ; free virtual = 48807 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 22390 ; free virtual = 48792 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 511.531 ; free physical = 22394 ; free virtual = 48796 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 22393 ; free virtual = 48795 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:02:03 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 244 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2473.363 ; gain = 345.105 ; free physical = 22106 ; free virtual = 48509 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:02:04 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs DONE Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_008 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.230 ; gain = 0.000 ; free physical = 22728 ; free virtual = 49131 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1908.461 ; gain = 0.000 ; free physical = 22658 ; free virtual = 49061 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.273 ; gain = 509.531 ; free physical = 22651 ; free virtual = 49054 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.273 ; gain = 509.531 ; free physical = 22647 ; free virtual = 49050 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.273 ; gain = 509.531 ; free physical = 22642 ; free virtual = 49046 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.273 ; gain = 509.531 ; free physical = 22636 ; free virtual = 49039 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.273 ; gain = 509.531 ; free physical = 22635 ; free virtual = 49038 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1993.273 ; gain = 509.531 ; free physical = 22630 ; free virtual = 49033 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1993.273 ; gain = 576.562 ; free physical = 22630 ; free virtual = 49033 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1e0a71f46 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 22588 ; free virtual = 48991 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 277f9852c Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 22585 ; free virtual = 48988 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 277f9852c Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 22571 ; free virtual = 48974 Phase 1 Placer Initialization | Checksum: 277f9852c Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1996.504 ; gain = 507.531 ; free physical = 22570 ; free virtual = 48973 Phase 2 Global Placement INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 31871 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 2 Global Placement | Checksum: 26fe28def Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22275 ; free virtual = 48678 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: 26fe28def Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22272 ; free virtual = 48676 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2433660c9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22271 ; free virtual = 48674 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 21d113e94 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22266 ; free virtual = 48670 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1e6c59ef9 Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22266 ; free virtual = 48669 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22232 ; free virtual = 48636 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22230 ; free virtual = 48633 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22229 ; free virtual = 48632 Phase 3 Detail Placement | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22229 ; free virtual = 48632 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22227 ; free virtual = 48631 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22225 ; free virtual = 48628 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22225 ; free virtual = 48628 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22224 ; free virtual = 48627 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2192340da Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22224 ; free virtual = 48627 Ending Placer Task | Checksum: 1d0f627a1 Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2084.547 ; gain = 595.574 ; free physical = 22235 ; free virtual = 48638 25 Infos, 104 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:28 . Memory (MB): peak = 2084.547 ; gain = 659.605 ; free physical = 22234 ; free virtual = 48638 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Creating bitstream... WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: ec567e97 ConstDB: 0 ShapeSum: e49fa90a RouteDB: 0 Phase 1 Build RT Design ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 21923 ; free virtual = 48326 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32526 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/top.v:2] Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.180 ; gain = 43.668 ; free physical = 22165 ; free virtual = 48572 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.168 ; gain = 50.656 ; free physical = 22137 ; free virtual = 48546 Phase 2.2 Pre Route Cleanup --------------------------------------------------------------------------------- Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2074.168 ; gain = 50.656 ; free physical = 22137 ; free virtual = 48544 Finished Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 22137 ; free virtual = 48544 --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32561 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 22102 ; free virtual = 48510 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 22101 ; free virtual = 48509 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 22113 ; free virtual = 48521 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.598 ; gain = 63.086 ; free physical = 22079 ; free virtual = 48487 Phase 3 Initial Routing Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.598 ; gain = 63.086 ; free physical = 21976 ; free virtual = 48384 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.598 ; gain = 63.086 ; free physical = 21965 ; free virtual = 48372 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.598 ; gain = 63.086 ; free physical = 21962 ; free virtual = 48370 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.598 ; gain = 63.086 ; free physical = 21961 ; free virtual = 48369 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.598 ; gain = 63.086 ; free physical = 21961 ; free virtual = 48369 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.598 ; gain = 63.086 ; free physical = 21960 ; free virtual = 48368 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2086.598 ; gain = 63.086 ; free physical = 21953 ; free virtual = 48360 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.598 ; gain = 65.086 ; free physical = 21951 ; free virtual = 48359 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.598 ; gain = 66.086 ; free physical = 21915 ; free virtual = 48323 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2089.598 ; gain = 66.086 ; free physical = 21949 ; free virtual = 48357 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2128.387 ; gain = 136.891 ; free physical = 21949 ; free virtual = 48357 Writing placer database... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32604 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2128.387 ; gain = 0.000 ; free physical = 21907 ; free virtual = 48318 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:02:21 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:42 . Memory (MB): peak = 2607.273 ; gain = 389.121 ; free physical = 21825 ; free virtual = 48233 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:02:21 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 32730 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading data files... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 22558 ; free virtual = 48966 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 22552 ; free virtual = 48960 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 22553 ; free virtual = 48962 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:38 ; elapsed = 00:00:40 . Memory (MB): peak = 2063.926 ; gain = 44.668 ; free physical = 22480 ; free virtual = 48889 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:38 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.914 ; gain = 50.656 ; free physical = 22414 ; free virtual = 48822 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:38 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.914 ; gain = 50.656 ; free physical = 22409 ; free virtual = 48817 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.445 ; gain = 60.824 ; free physical = 22376 ; free virtual = 48785 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 22342 ; free virtual = 48751 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 22334 ; free virtual = 48742 Phase 2 Router Initialization | Checksum: 117ddc37d --------------------------------------------------------------------------------- Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 22334 ; free virtual = 48742 Phase 3 Initial Routing Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 22334 ; free virtual = 48742 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 22333 ; free virtual = 48742 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 22333 ; free virtual = 48741 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 22333 ; free virtual = 48741 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 22333 ; free virtual = 48741 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 22333 ; free virtual = 48741 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 22330 ; free virtual = 48738 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 22332 ; free virtual = 48740 INFO: [Project 1-571] Translating synthesized netlist ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2081.969 ; gain = 62.711 ; free physical = 22278 ; free virtual = 48686 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2081.969 ; gain = 62.711 ; free physical = 22270 ; free virtual = 48679 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2081.969 ; gain = 62.711 ; free physical = 22269 ; free virtual = 48678 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2081.969 ; gain = 62.711 ; free physical = 22268 ; free virtual = 48677 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2081.969 ; gain = 62.711 ; free physical = 22266 ; free virtual = 48675 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2081.969 ; gain = 62.711 ; free physical = 22266 ; free virtual = 48674 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.969 ; gain = 62.711 ; free physical = 22237 ; free virtual = 48645 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2083.969 ; gain = 64.711 ; free physical = 22237 ; free virtual = 48646 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2083.969 ; gain = 64.711 ; free physical = 22230 ; free virtual = 48639 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2083.969 ; gain = 64.711 ; free physical = 22266 ; free virtual = 48675 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:43 . Memory (MB): peak = 2122.758 ; gain = 135.516 ; free physical = 22266 ; free virtual = 48674 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2122.758 ; gain = 0.000 ; free physical = 22246 ; free virtual = 48657 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:475] Command: synth_design -top top WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:490] Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 22138 ; free virtual = 48547 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 310 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:16] 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 21925 ; free virtual = 48334 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:16] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/top.v:2] WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 21970 ; free virtual = 48382 --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 21990 ; free virtual = 48406 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 21989 ; free virtual = 48405 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 21990 ; free virtual = 48400 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.953 ; gain = 132.332 ; free physical = 21951 ; free virtual = 48368 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1235.980 ; gain = 140.359 ; free physical = 21954 ; free virtual = 48371 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Loading data files... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 21939 ; free virtual = 48349 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 21939 ; free virtual = 48349 --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:16] INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.562 ; gain = 81.648 ; free physical = 21850 ; free virtual = 48260 --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 21565 ; free virtual = 47976 --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 21553 ; free virtual = 47964 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 21541 ; free virtual = 47952 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Loading route data... Processing options... Creating bitmap... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 21400 ; free virtual = 47811 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1267.973 ; gain = 172.352 ; free physical = 21391 ; free virtual = 47802 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 21341 ; free virtual = 47751 --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 21223 ; free virtual = 47633 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:18] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 21190 ; free virtual = 47602 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 21169 ; free virtual = 47580 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 21168 ; free virtual = 47579 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 21169 ; free virtual = 47580 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 21262 ; free virtual = 47677 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.559 ; gain = 248.938 ; free physical = 21260 ; free virtual = 47675 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 21240 ; free virtual = 47656 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 21219 ; free virtual = 47634 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 21121 ; free virtual = 47536 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21087 ; free virtual = 47502 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading site data... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 21019 ; free virtual = 47435 --------------------------------------------------------------------------------- INFO: Helper process launched with PID 423 Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 21010 ; free virtual = 47425 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1343.551 ; gain = 247.938 ; free physical = 21003 ; free virtual = 47418 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 21001 ; free virtual = 47416 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 21000 ; free virtual = 47416 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 21000 ; free virtual = 47416 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 21000 ; free virtual = 47416 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 21000 ; free virtual = 47415 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 20999 ; free virtual = 47414 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.590 ; gain = 269.961 ; free physical = 21001 ; free virtual = 47416 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21001 ; free virtual = 47416 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21006 ; free virtual = 47421 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20994 ; free virtual = 47409 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20992 ; free virtual = 47407 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20991 ; free virtual = 47407 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20991 ; free virtual = 47406 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20990 ; free virtual = 47406 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:23 . Memory (MB): peak = 1343.551 ; gain = 247.938 ; free physical = 20989 ; free virtual = 47405 Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20990 ; free virtual = 47405 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 20991 ; free virtual = 47406 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:02:43 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Project 1-571] Translating synthesized netlist 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2463.562 ; gain = 335.176 ; free physical = 20984 ; free virtual = 47399 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:02:43 2019... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 21098 ; free virtual = 47513 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_011 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 21840 ; free virtual = 48255 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 21839 ; free virtual = 48254 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 21838 ; free virtual = 48253 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 21838 ; free virtual = 48253 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 21838 ; free virtual = 48253 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 21853 ; free virtual = 48269 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 21893 ; free virtual = 48308 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.574 ; gain = 268.961 ; free physical = 21896 ; free virtual = 48311 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.582 ; gain = 268.961 ; free physical = 21896 ; free virtual = 48312 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: 15c4992dc Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2069.957 ; gain = 43.668 ; free physical = 21866 ; free virtual = 48281 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15c4992dc Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2075.945 ; gain = 49.656 ; free physical = 21822 ; free virtual = 48237 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15c4992dc Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2075.945 ; gain = 49.656 ; free physical = 21820 ; free virtual = 48236 Phase 1 Build RT Design | Checksum: 18a962264 Time (s): cpu = 00:00:39 ; elapsed = 00:00:37 . Memory (MB): peak = 2066.957 ; gain = 41.668 ; free physical = 21790 ; free virtual = 48205 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 18a962264 Time (s): cpu = 00:00:39 ; elapsed = 00:00:37 . Memory (MB): peak = 2073.945 ; gain = 48.656 ; free physical = 21746 ; free virtual = 48162 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 18a962264 Time (s): cpu = 00:00:39 ; elapsed = 00:00:37 . Memory (MB): peak = 2073.945 ; gain = 48.656 ; free physical = 21745 ; free virtual = 48161 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b213fb45 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 21693 ; free virtual = 48109 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10fb680fc Time (s): cpu = 00:00:40 ; elapsed = 00:00:38 . Memory (MB): peak = 2086.250 ; gain = 60.961 ; free physical = 21671 ; free virtual = 48089 Phase 3 Initial Routing Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 21693 ; free virtual = 48109 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 21686 ; free virtual = 48102 Phase 4 Rip-up And Reroute | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 21686 ; free virtual = 48101 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 21685 ; free virtual = 48101 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Number of Nodes with overlaps = 0 Phase 6.1 Hold Fix Iter | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 21685 ; free virtual = 48101 Phase 3 Initial Routing | Checksum: 10fb680fc Time (s): cpu = 00:00:40 ; elapsed = 00:00:38 . Memory (MB): peak = 2087.250 ; gain = 61.961 ; free physical = 21685 ; free virtual = 48100 Phase 6 Post Hold Fix | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 21685 ; free virtual = 48100 INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 7 Route finalize Phase 4.1 Global Iteration 0 | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:38 . Memory (MB): peak = 2087.250 ; gain = 61.961 ; free physical = 21681 ; free virtual = 48096 Phase 4 Rip-up And Reroute | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:38 . Memory (MB): peak = 2087.250 ; gain = 61.961 ; free physical = 21680 ; free virtual = 48095 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:38 . Memory (MB): peak = 2087.250 ; gain = 61.961 ; free physical = 21679 ; free virtual = 48095 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Phase 6.1 Hold Fix Iter | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:38 . Memory (MB): peak = 2087.250 ; gain = 61.961 ; free physical = 21678 ; free virtual = 48094 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 21677 ; free virtual = 48093 --------------------------------------------------------------------------------- Phase 6 Post Hold Fix | Checksum: 10fb680fc Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2087.250 ; gain = 61.961 ; free physical = 21677 ; free virtual = 48093 *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2089.375 ; gain = 63.086 ; free physical = 21674 ; free virtual = 48090 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 21671 ; free virtual = 48087 Phase 9 Depositing Routes Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Phase 7 Route finalize | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2087.250 ; gain = 61.961 ; free physical = 21672 ; free virtual = 48088 Phase 8 Verifying routed nets INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/top.v:2] Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 21672 ; free virtual = 48087 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1b213fb45 Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2092.375 ; gain = 66.086 ; free physical = 21673 ; free virtual = 48089 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2092.375 ; gain = 66.086 ; free physical = 21709 ; free virtual = 48125 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2131.164 ; gain = 136.891 ; free physical = 21712 ; free virtual = 48127 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.691 ; gain = 211.238 ; free physical = 21729 ; free virtual = 48144 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 9 Depositing Routes | Checksum: 10fb680fc Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 21729 ; free virtual = 48144 --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:39 . Memory (MB): peak = 2090.250 ; gain = 64.961 ; free physical = 21766 ; free virtual = 48181 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:41 . Memory (MB): peak = 2129.039 ; gain = 135.766 ; free physical = 21759 ; free virtual = 48175 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 21773 ; free virtual = 48189 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing placer database... Writing placer database... INFO: [Project 1-570] Preparing netlist for logic optimization Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2129.039 ; gain = 0.000 ; free physical = 21794 ; free virtual = 48224 Write XDEF Complete: Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2131.164 ; gain = 0.000 ; free physical = 21784 ; free virtual = 48216 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 21510 ; free virtual = 47948 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 21504 ; free virtual = 47942 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 21496 ; free virtual = 47934 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 21494 ; free virtual = 47932 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 21490 ; free virtual = 47928 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 21489 ; free virtual = 47927 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 21489 ; free virtual = 47927 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 21514 ; free virtual = 47933 --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 21517 ; free virtual = 47936 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.676 ; gain = 219.215 ; free physical = 21524 ; free virtual = 47942 INFO: [Project 1-571] Translating synthesized netlist Creating bitstream... Running DRC as a precondition to command write_bitstream Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 21280 ; free virtual = 47719 INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.070 ; gain = 230.156 ; free physical = 21292 ; free virtual = 47710 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1334.098 ; gain = 238.184 ; free physical = 21291 ; free virtual = 47710 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 21115 ; free virtual = 47533 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 21127 ; free virtual = 47546 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 21127 ; free virtual = 47546 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 21127 ; free virtual = 47545 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 21126 ; free virtual = 47545 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 21125 ; free virtual = 47544 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 21125 ; free virtual = 47544 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 21341 ; free virtual = 47763 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 10fbb77b1 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2084.547 ; gain = 0.000 ; free physical = 21245 ; free virtual = 47668 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 10fbb77b1 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2084.547 ; gain = 0.000 ; free physical = 21204 ; free virtual = 47626 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10fbb77b1 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2084.547 ; gain = 0.000 ; free physical = 21205 ; free virtual = 47628 Starting Routing Task INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 174384e93 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 21082 ; free virtual = 47505 Phase 3 Initial Routing INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 1467.254 ; gain = 384.359 ; free physical = 21124 ; free virtual = 47547 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Loading data files... INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 706f0e10 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 21115 ; free virtual = 47538 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 706f0e10 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 21113 ; free virtual = 47536 Command: report_drc (run_mandatory_drcs) for: placer_checks Phase 4 Rip-up And Reroute | Checksum: 706f0e10 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 21113 ; free virtual = 47536 Phase 5 Delay and Skew Optimization INFO: [DRC 23-27] Running DRC with 8 threads Phase 5 Delay and Skew Optimization | Checksum: 706f0e10 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 21112 ; free virtual = 47535 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 706f0e10 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 21112 ; free virtual = 47535 Phase 6 Post Hold Fix | Checksum: 706f0e10 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 21111 ; free virtual = 47534 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00352076 % Global Horizontal Routing Utilization = 0.00439486 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. South Dir 1x1 Area, Max Cong = 1.8018%, No Congested Regions. East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 706f0e10 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 21095 ; free virtual = 47518 Phase 8 Verifying routed nets Verification completed successfully INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 8 Verifying routed nets | Checksum: 706f0e10 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 21093 ; free virtual = 47515 Phase 9 Depositing Routes INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 9 Depositing Routes | Checksum: 706f0e10 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 21080 ; free virtual = 47503 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2101.234 ; gain = 16.688 ; free physical = 21117 ; free virtual = 47540 Routing Is Done. 32 Infos, 105 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2140.023 ; gain = 55.477 ; free physical = 21118 ; free virtual = 47541 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1405.684 ; gain = 322.789 ; free physical = 21136 ; free virtual = 47559 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 1468.250 ; gain = 385.359 ; free physical = 21131 ; free virtual = 47554 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:90] Command: report_drc (run_mandatory_drcs) for: incr_eco_checks WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:1575] Writing placer database... INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/top.v:2] Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2140.023 ; gain = 0.000 ; free physical = 21128 ; free virtual = 47553 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 21139 ; free virtual = 47565 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 21121 ; free virtual = 47545 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 21120 ; free virtual = 47544 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 21049 ; free virtual = 47473 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:02:55 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:28 . Memory (MB): peak = 2460.863 ; gain = 338.105 ; free physical = 21024 ; free virtual = 47448 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:02:55 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1550.285 ; gain = 0.000 ; free physical = 21172 ; free virtual = 47596 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.715 ; gain = 0.000 ; free physical = 21982 ; free virtual = 48405 Bitstream size: 4243411 bytes Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1470.715 ; gain = 0.000 ; free physical = 21978 ; free virtual = 48401 Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.53 . Memory (MB): peak = 1550.285 ; gain = 0.000 ; free physical = 21978 ; free virtual = 48402 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 1336.066 ; gain = 240.152 ; free physical = 21954 ; free virtual = 48378 --------------------------------------------------------------------------------- Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1545.953 ; gain = 0.000 ; free physical = 21930 ; free virtual = 48353 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 21925 ; free virtual = 48349 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1545.953 ; gain = 0.000 ; free physical = 21934 ; free virtual = 48358 INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1544.949 ; gain = 0.000 ; free physical = 21680 ; free virtual = 48105 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1544.949 ; gain = 0.000 ; free physical = 21687 ; free virtual = 48111 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 1346.098 ; gain = 250.184 ; free physical = 21640 ; free virtual = 48065 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 1346.098 ; gain = 250.184 ; free physical = 21541 ; free virtual = 47966 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 1354.074 ; gain = 258.160 ; free physical = 21345 ; free virtual = 47770 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 1354.074 ; gain = 258.160 ; free physical = 21197 ; free virtual = 47622 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 1354.074 ; gain = 258.160 ; free physical = 21169 ; free virtual = 47593 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 1354.074 ; gain = 258.160 ; free physical = 21093 ; free virtual = 47518 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1354.074 ; gain = 258.160 ; free physical = 21073 ; free virtual = 47503 --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1354.074 ; gain = 258.160 ; free physical = 21073 ; free virtual = 47498 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1354.074 ; gain = 258.160 ; free physical = 21067 ; free virtual = 47491 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1354.074 ; gain = 258.160 ; free physical = 21065 ; free virtual = 47490 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1354.074 ; gain = 258.160 ; free physical = 21060 ; free virtual = 47485 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1354.082 ; gain = 258.160 ; free physical = 21061 ; free virtual = 47485 INFO: [Project 1-571] Translating synthesized netlist No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 21006 ; free virtual = 47430 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1303.684 ; gain = 208.242 ; free physical = 21003 ; free virtual = 47427 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 20997 ; free virtual = 47422 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading route data... Loading route data... Processing options... Creating bitmap... Processing options... Creating bitmap... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 20885 ; free virtual = 47309 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 20884 ; free virtual = 47309 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 20883 ; free virtual = 47308 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 20883 ; free virtual = 47308 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 20883 ; free virtual = 47308 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 20883 ; free virtual = 47307 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 20883 ; free virtual = 47307 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.660 ; gain = 216.219 ; free physical = 20882 ; free virtual = 47307 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.668 ; gain = 216.219 ; free physical = 20883 ; free virtual = 47307 INFO: [Project 1-571] Translating synthesized netlist Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: Helper process launched with PID 838 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:28 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 20601 ; free virtual = 47025 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 20420 ; free virtual = 46845 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 20420 ; free virtual = 46845 INFO: [Project 1-570] Preparing netlist for logic optimization Loading site data... Creating bitstream... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing bitstream ./design.bit... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1898.203 ; gain = 0.000 ; free physical = 19967 ; free virtual = 46400 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 515.531 ; free physical = 20111 ; free virtual = 46544 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 515.531 ; free physical = 20092 ; free virtual = 46525 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 515.531 ; free physical = 20076 ; free virtual = 46509 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 515.531 ; free physical = 20064 ; free virtual = 46497 Phase 2 Final Placement Cleanup INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 515.531 ; free physical = 20054 ; free virtual = 46487 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.246 ; gain = 515.531 ; free physical = 20044 ; free virtual = 46477 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1986.246 ; gain = 580.562 ; free physical = 20040 ; free virtual = 46473 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 19895 ; free virtual = 46328 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 19884 ; free virtual = 46317 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.773 ; gain = 0.000 ; free physical = 19785 ; free virtual = 46217 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string # source "$::env(XRAY_DIR)/utils/utils.tcl" Parameter USE_SIMD bound to: ONE48 - type: string ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:232] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/top.v:2] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 19579 ; free virtual = 46012 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 19535 ; free virtual = 45968 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:03:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 19559 ; free virtual = 45992 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 19562 ; free virtual = 45996 --------------------------------------------------------------------------------- 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:31 . Memory (MB): peak = 2470.270 ; gain = 339.105 ; free physical = 19564 ; free virtual = 45998 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:03:19 2019... INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 19575 ; free virtual = 46007 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.488 ; gain = 453.203 ; free physical = 20513 ; free virtual = 46946 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1904.438 ; gain = 0.000 ; free physical = 20499 ; free virtual = 46933 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_009 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 1048 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:03:20 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:32 . Memory (MB): peak = 2469.145 ; gain = 340.105 ; free physical = 20441 ; free virtual = 46876 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:03:20 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Writing bitstream ./design.bit... touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_010 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.152 ; gain = 458.203 ; free physical = 21678 ; free virtual = 48123 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 21667 ; free virtual = 48112 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 21662 ; free virtual = 48107 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 457.203 ; free physical = 21707 ; free virtual = 48153 Phase 2 Global Placement Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.488 ; gain = 453.203 ; free physical = 21655 ; free virtual = 48101 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.488 ; gain = 453.203 ; free physical = 21651 ; free virtual = 48097 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.488 ; gain = 453.203 ; free physical = 21644 ; free virtual = 48090 Phase 2 Global Placement WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:03:24 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 106 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2476.129 ; gain = 336.105 ; free physical = 21539 ; free virtual = 47985 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 458.203 ; free physical = 21540 ; free virtual = 47987 Phase 1.4 Constrain Clocks/Macros INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:03:24 2019... Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 21589 ; free virtual = 48035 Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 458.203 ; free physical = 21606 ; free virtual = 48052 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.152 ; gain = 458.203 ; free physical = 22517 ; free virtual = 48963 Phase 2 Global Placement Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22511 ; free virtual = 48957 Phase 3.2 Commit Most Macros & LUTRAMs WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer touch build/specimen_012/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22477 ; free virtual = 48923 Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 12 #of bits: 22337 #of tags: 140 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram' GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_009 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22413 ; free virtual = 48863 Phase 3.4 Pipeline Register Optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22365 ; free virtual = 48811 Phase 3.5 Small Shape Detail Placement Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22363 ; free virtual = 48810 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 22340 ; free virtual = 48787 --------------------------------------------------------------------------------- Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22337 ; free virtual = 48784 Phase 3.2 Commit Most Macros & LUTRAMs Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 22330 ; free virtual = 48777 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22382 ; free virtual = 48828 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22377 ; free virtual = 48824 Phase 3.3 Area Swap Optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22364 ; free virtual = 48811 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22357 ; free virtual = 48804 Phase 3.5 Small Shape Detail Placement INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22360 ; free virtual = 48807 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22365 ; free virtual = 48812 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22374 ; free virtual = 48821 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22380 ; free virtual = 48827 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22384 ; free virtual = 48831 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22387 ; free virtual = 48834 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:05 . Memory (MB): peak = 1476.832 ; gain = 393.945 ; free physical = 22389 ; free virtual = 48836 |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22389 ; free virtual = 48836 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 22387 ; free virtual = 48834 INFO: [DRC 23-27] Running DRC with 8 threads Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 22390 ; free virtual = 48837 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.438 ; gain = 55.992 ; free physical = 22370 ; free virtual = 48817 --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22363 ; free virtual = 48810 Phase 3.6 Re-assign LUT pins Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 22344 ; free virtual = 48791 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22335 ; free virtual = 48782 Phase 3.7 Pipeline Register Optimization Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 22307 ; free virtual = 48754 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22296 ; free virtual = 48743 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22255 ; free virtual = 48702 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 22236 ; free virtual = 48683 Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22236 ; free virtual = 48683 Phase 4.2 Post Placement Cleanup Phase 3.3 Area Swap Optimization Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22213 ; free virtual = 48659 Phase 4.3 Placer Reporting Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22210 ; free virtual = 48657 Phase 3.6 Re-assign LUT pins Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 22206 ; free virtual = 48653 Phase 3.4 Pipeline Register Optimization INFO: [Project 1-570] Preparing netlist for logic optimization Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22191 ; free virtual = 48638 Phase 4.4 Final Placement Cleanup Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22190 ; free virtual = 48637 Phase 3.7 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 22182 ; free virtual = 48629 Phase 3.5 Small Shape Detail Placement INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2] Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22125 ; free virtual = 48572 Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22121 ; free virtual = 48567 Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22057 ; free virtual = 48504 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22059 ; free virtual = 48506 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 553.250 ; free physical = 22042 ; free virtual = 48489 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 630.953 ; free physical = 22042 ; free virtual = 48489 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22038 ; free virtual = 48485 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.2 Post Placement Cleanup Phase 1 Placer Initialization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.1 Placer Initialization Netlist Sorting INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 22004 ; free virtual = 48451 WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1505] Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1559.863 ; gain = 0.000 ; free physical = 22003 ; free virtual = 48450 WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/top.v:2] Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.47 . Memory (MB): peak = 1559.863 ; gain = 0.000 ; free physical = 22017 ; free virtual = 48464 Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22016 ; free virtual = 48466 Phase 4.3 Placer Reporting --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 21970 ; free virtual = 48417 --------------------------------------------------------------------------------- Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 21964 ; free virtual = 48411 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22001 ; free virtual = 48455 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1211.945 ; gain = 116.500 ; free physical = 22013 ; free virtual = 48461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 22015 ; free virtual = 48463 --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 22031 ; free virtual = 48479 Phase 3.6 Re-assign LUT pins INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22013 ; free virtual = 48460 Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 22043 ; free virtual = 48491 Phase 3.7 Pipeline Register Optimization Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.531 ; gain = 541.246 ; free physical = 22088 ; free virtual = 48536 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.531 ; gain = 624.277 ; free physical = 22087 ; free virtual = 48535 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 22071 ; free virtual = 48518 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 22049 ; free virtual = 48497 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 22001 ; free virtual = 48449 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 22000 ; free virtual = 48447 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 21998 ; free virtual = 48446 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 21996 ; free virtual = 48443 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 21995 ; free virtual = 48442 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 21994 ; free virtual = 48441 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:12 . Memory (MB): peak = 1219.973 ; gain = 124.527 ; free physical = 21986 ; free virtual = 48433 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 21973 ; free virtual = 48420 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 21819 ; free virtual = 48267 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 21839 ; free virtual = 48286 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully Phase 4.3 Placer Reporting INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 21793 ; free virtual = 48241 Phase 4.4 Final Placement Cleanup Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 21839 ; free virtual = 48286 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 21754 ; free virtual = 48201 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.199 ; gain = 554.250 ; free physical = 21844 ; free virtual = 48291 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.199 ; gain = 631.953 ; free physical = 21842 ; free virtual = 48289 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 21851 ; free virtual = 48299 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Starting Routing Task INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 126a650e7 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 21749 ; free virtual = 48197 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 126a650e7 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 21721 ; free virtual = 48168 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 126a650e7 Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2061.922 ; gain = 97.656 ; free physical = 21721 ; free virtual = 48169 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 96eb7d44 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 21742 ; free virtual = 48190 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1470.961 ; gain = 0.000 ; free physical = 21742 ; free virtual = 48189 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 21741 ; free virtual = 48189 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1470.961 ; gain = 0.000 ; free physical = 21740 ; free virtual = 48187 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 21740 ; free virtual = 48187 Phase 4 Rip-up And Reroute | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 21740 ; free virtual = 48187 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 21740 ; free virtual = 48187 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 21740 ; free virtual = 48187 Phase 6 Post Hold Fix | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 21740 ; free virtual = 48187 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2068.977 ; gain = 104.711 ; free physical = 21730 ; free virtual = 48177 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 21729 ; free virtual = 48176 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 96eb7d44 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 21728 ; free virtual = 48176 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2071.977 ; gain = 107.711 ; free physical = 21761 ; free virtual = 48208 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2110.766 ; gain = 178.516 ; free physical = 21761 ; free virtual = 48208 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2110.766 ; gain = 0.000 ; free physical = 21756 ; free virtual = 48205 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 21444 ; free virtual = 47892 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1311.684 ; gain = 216.238 ; free physical = 21392 ; free virtual = 47840 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21374 ; free virtual = 47822 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21090 ; free virtual = 47538 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21089 ; free virtual = 47536 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21085 ; free virtual = 47532 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21084 ; free virtual = 47532 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21084 ; free virtual = 47532 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21083 ; free virtual = 47531 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21082 ; free virtual = 47529 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.668 ; gain = 225.223 ; free physical = 21080 ; free virtual = 47528 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 1320.676 ; gain = 225.223 ; free physical = 21081 ; free virtual = 47529 INFO: [Project 1-571] Translating synthesized netlist Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3599 INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3603 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 3684 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1416.707 ; gain = 333.820 ; free physical = 20424 ; free virtual = 46872 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1481.738 ; gain = 0.000 ; free physical = 20189 ; free virtual = 46637 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1481.738 ; gain = 0.000 ; free physical = 20190 ; free virtual = 46638 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Loading site data... Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.352 ; gain = 0.000 ; free physical = 19956 ; free virtual = 46403 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Loading route data... Processing options... Creating bitmap... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 19870 ; free virtual = 46318 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 19768 ; free virtual = 46216 --------------------------------------------------------------------------------- Creating bitstream... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 19714 ; free virtual = 46162 Phase 1.3 Build Placer Netlist Model INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.449 ; gain = 0.000 ; free physical = 19419 ; free virtual = 45867 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.492 ; gain = 519.531 ; free physical = 19404 ; free virtual = 45852 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.492 ; gain = 519.531 ; free physical = 19403 ; free virtual = 45851 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.492 ; gain = 519.531 ; free physical = 19402 ; free virtual = 45850 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.492 ; gain = 519.531 ; free physical = 19401 ; free virtual = 45849 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.492 ; gain = 519.531 ; free physical = 19398 ; free virtual = 45846 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Writing bitstream ./design.bit... Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1990.492 ; gain = 519.531 ; free physical = 19400 ; free virtual = 45848 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1990.492 ; gain = 583.562 ; free physical = 19400 ; free virtual = 45848 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 19527 ; free virtual = 45979 --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:16] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/top.v:2] Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 19601 ; free virtual = 46053 Phase 1.4 Constrain Clocks/Macros INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:13] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2061.930 ; gain = 43.668 ; free physical = 19617 ; free virtual = 46072 Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:73] Phase 2 Router Initialization WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:73] INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:253] Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:308] Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 19584 ; free virtual = 46042 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:333] Phase 2.1 Fix Topology Constraints WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:358] Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:363] Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.918 ; gain = 49.656 ; free physical = 19580 ; free virtual = 46039 Phase 2.2 Pre Route Cleanup WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:393] Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:398] Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.918 ; gain = 49.656 ; free physical = 19580 ; free virtual = 46039 WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 19575 ; free virtual = 46028 --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 19579 ; free virtual = 46032 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 19635 ; free virtual = 46092 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 19643 ; free virtual = 46103 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2077.973 ; gain = 59.711 ; free physical = 19647 ; free virtual = 46106 Phase 3 Initial Routing Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.395 ; gain = 492.531 ; free physical = 19636 ; free virtual = 46099 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.395 ; gain = 575.562 ; free physical = 19630 ; free virtual = 46093 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 19632 ; free virtual = 46092 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 19632 ; free virtual = 46091 --------------------------------------------------------------------------------- Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 19635 ; free virtual = 46089 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 19636 ; free virtual = 46089 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 19631 ; free virtual = 46084 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 19635 ; free virtual = 46089 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 19635 ; free virtual = 46089 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 19635 ; free virtual = 46089 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 19635 ; free virtual = 46089 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 19635 ; free virtual = 46089 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 19635 ; free virtual = 46088 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2079.973 ; gain = 61.711 ; free physical = 19623 ; free virtual = 46077 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.973 ; gain = 63.711 ; free physical = 19621 ; free virtual = 46074 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.973 ; gain = 63.711 ; free physical = 19585 ; free virtual = 46038 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2081.973 ; gain = 63.711 ; free physical = 19620 ; free virtual = 46073 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:42 . Memory (MB): peak = 2120.762 ; gain = 134.516 ; free physical = 19618 ; free virtual = 46072 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:03:59 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Write XDEF Complete: Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2120.762 ; gain = 0.000 ; free physical = 19546 ; free virtual = 46001 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 2453.871 ; gain = 343.105 ; free physical = 19550 ; free virtual = 46006 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:03:59 2019... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_011 Running DRC as a precondition to command write_bitstream report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [DRC 23-27] Running DRC with 8 threads Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 20372 ; free virtual = 46826 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 19950 ; free virtual = 46405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:23 . Memory (MB): peak = 1343.555 ; gain = 247.938 ; free physical = 19938 ; free virtual = 46393 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1343.555 ; gain = 247.938 ; free physical = 19973 ; free virtual = 46430 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 19941 ; free virtual = 46400 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 19926 ; free virtual = 46386 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 19904 ; free virtual = 46379 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 19889 ; free virtual = 46345 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 19872 ; free virtual = 46329 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 19869 ; free virtual = 46326 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 19866 ; free virtual = 46323 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 19866 ; free virtual = 46322 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 19865 ; free virtual = 46321 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 19865 ; free virtual = 46321 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 19864 ; free virtual = 46320 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 19862 ; free virtual = 46319 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 19864 ; free virtual = 46320 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 19691 ; free virtual = 46167 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 19656 ; free virtual = 46131 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 19634 ; free virtual = 46109 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 19632 ; free virtual = 46108 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 19631 ; free virtual = 46106 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 19630 ; free virtual = 46105 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 19629 ; free virtual = 46105 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1364.578 ; gain = 268.961 ; free physical = 19629 ; free virtual = 46105 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1364.586 ; gain = 268.961 ; free physical = 19631 ; free virtual = 46106 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.227 ; gain = 0.000 ; free physical = 19559 ; free virtual = 46035 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 19555 ; free virtual = 46011 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 19554 ; free virtual = 46010 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 19553 ; free virtual = 46009 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 19540 ; free virtual = 45997 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 19536 ; free virtual = 45992 INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 19535 ; free virtual = 45991 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 19529 ; free virtual = 45986 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1994.270 ; gain = 512.531 ; free physical = 19529 ; free virtual = 45986 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1994.270 ; gain = 577.562 ; free physical = 19529 ; free virtual = 45985 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2130.430 ; gain = 31.227 ; free physical = 19260 ; free virtual = 45716 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2136.418 ; gain = 37.215 ; free physical = 19213 ; free virtual = 45670 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2136.418 ; gain = 37.215 ; free physical = 19213 ; free virtual = 45670 Phase 1 Build RT Design | Checksum: 12e08b258 Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2056.930 ; gain = 92.668 ; free physical = 19106 ; free virtual = 45562 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 12e08b258 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2063.918 ; gain = 99.656 ; free physical = 19067 ; free virtual = 45524 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 12e08b258 Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2063.918 ; gain = 99.656 ; free physical = 19067 ; free virtual = 45523 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:39 . Memory (MB): peak = 2129.965 ; gain = 38.434 ; free physical = 19104 ; free virtual = 45560 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 19058 ; free virtual = 45514 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 106d813e1 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 19055 ; free virtual = 45512 Phase 3 Initial Routing Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2135.953 ; gain = 44.422 ; free physical = 19055 ; free virtual = 45511 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2135.953 ; gain = 44.422 ; free physical = 19054 ; free virtual = 45511 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 19037 ; free virtual = 45493 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 19045 ; free virtual = 45501 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 19045 ; free virtual = 45501 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 19045 ; free virtual = 45501 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 19045 ; free virtual = 45501 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 19044 ; free virtual = 45500 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 19056 ; free virtual = 45512 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 19054 ; free virtual = 45510 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 19047 ; free virtual = 45504 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 19046 ; free virtual = 45502 Phase 9 Depositing Routes INFO: [DRC 23-27] Running DRC with 8 threads Phase 4 Rip-up And Reroute Phase 9 Depositing Routes | Checksum: 8a792087 Phase 4.1 Global Iteration 0 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 19043 ; free virtual = 45499 Phase 4.1 Global Iteration 0 | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 19047 ; free virtual = 45503 Phase 4 Rip-up And Reroute | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 19052 ; free virtual = 45508 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 19059 ; free virtual = 45515 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 19064 ; free virtual = 45520 Phase 6 Post Hold Fix | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.973 ; gain = 105.711 ; free physical = 19070 ; free virtual = 45526 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 19077 ; free virtual = 45534 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:44 . Memory (MB): peak = 2193.262 ; gain = 94.059 ; free physical = 19076 ; free virtual = 45532 Phase 7 Route finalize report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Loading site data... Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 7 Route finalize | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 19044 ; free virtual = 45501 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.973 ; gain = 109.711 ; free physical = 19040 ; free virtual = 45497 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 106d813e1 Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.973 ; gain = 109.711 ; free physical = 19037 ; free virtual = 45494 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2073.973 ; gain = 109.711 ; free physical = 19068 ; free virtual = 45525 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:42 . Memory (MB): peak = 2112.762 ; gain = 180.516 ; free physical = 19066 ; free virtual = 45523 Writing placer database... Writing placer database... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:40 . Memory (MB): peak = 2155.008 ; gain = 63.477 ; free physical = 19034 ; free virtual = 45491 Phase 3 Initial Routing Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2112.762 ; gain = 0.000 ; free physical = 19033 ; free virtual = 45492 Loading route data... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Processing options... Creating bitmap... INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 19008 ; free virtual = 45467 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.008 ; gain = 63.477 ; free physical = 19001 ; free virtual = 45461 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.008 ; gain = 63.477 ; free physical = 18989 ; free virtual = 45450 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.008 ; gain = 63.477 ; free physical = 18989 ; free virtual = 45450 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.008 ; gain = 63.477 ; free physical = 18989 ; free virtual = 45449 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.008 ; gain = 63.477 ; free physical = 18989 ; free virtual = 45449 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.008 ; gain = 63.477 ; free physical = 18989 ; free virtual = 45449 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.008 ; gain = 63.477 ; free physical = 18949 ; free virtual = 45411 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.008 ; gain = 63.477 ; free physical = 18946 ; free virtual = 45408 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.008 ; gain = 63.477 ; free physical = 18952 ; free virtual = 45414 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:41 . Memory (MB): peak = 2155.008 ; gain = 63.477 ; free physical = 18985 ; free virtual = 45447 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:43 . Memory (MB): peak = 2193.797 ; gain = 102.266 ; free physical = 18985 ; free virtual = 45446 Writing placer database... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 18986 ; free virtual = 45452 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1471.711 ; gain = 0.000 ; free physical = 18991 ; free virtual = 45457 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2131.426 ; gain = 32.227 ; free physical = 18988 ; free virtual = 45472 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2137.414 ; gain = 38.215 ; free physical = 18952 ; free virtual = 45437 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2137.414 ; gain = 38.215 ; free physical = 18952 ; free virtual = 45437 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.262 ; gain = 0.000 ; free physical = 18900 ; free virtual = 45394 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 18886 ; free virtual = 45381 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 18859 ; free virtual = 45357 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 18863 ; free virtual = 45360 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 18864 ; free virtual = 45361 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 18864 ; free virtual = 45362 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 18865 ; free virtual = 45362 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 18866 ; free virtual = 45363 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/design.dcp' has been generated. %, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. Command: write_bitstream -force design.bit East Dir Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 18918 ; free virtual = 45394 Phase 8 Verifying routed nets INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 18916 ; free virtual = 45392 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 18912 ; free virtual = 45390 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 2155.469 ; gain = 56.270 ; free physical = 18941 ; free virtual = 45421 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:45 . Memory (MB): peak = 2194.258 ; gain = 95.059 ; free physical = 18940 ; free virtual = 45420 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.797 ; gain = 0.000 ; free physical = 18803 ; free virtual = 45285 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1340.102 ; gain = 244.184 ; free physical = 18795 ; free virtual = 45284 --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1340.102 ; gain = 244.184 ; free physical = 18711 ; free virtual = 45180 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Creating bitstream... INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 18726 ; free virtual = 45201 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2194.258 ; gain = 0.000 ; free physical = 18593 ; free virtual = 45075 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 18590 ; free virtual = 45072 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1547.953 ; gain = 0.000 ; free physical = 18637 ; free virtual = 45097 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1547.953 ; gain = 0.000 ; free physical = 18570 ; free virtual = 45031 INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 4086 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 18536 ; free virtual = 44996 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 18572 ; free virtual = 45032 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 18498 ; free virtual = 44961 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 18466 ; free virtual = 44929 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 18446 ; free virtual = 44911 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 18445 ; free virtual = 44910 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 18452 ; free virtual = 44916 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1348.078 ; gain = 252.160 ; free physical = 18462 ; free virtual = 44926 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1348.086 ; gain = 252.160 ; free physical = 18465 ; free virtual = 44930 INFO: [Project 1-571] Translating synthesized netlist INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:04:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:29 . Memory (MB): peak = 2460.867 ; gain = 340.105 ; free physical = 18377 ; free virtual = 44841 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:04:28 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. Loading route data... Processing options... Creating bitmap... INFO: [Project 1-570] Preparing netlist for logic optimization Creating bitstream... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1156.438 ; gain = 60.824 ; free physical = 18831 ; free virtual = 45297 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1899.199 ; gain = 0.000 ; free physical = 18302 ; free virtual = 44769 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Writing bitstream ./design.bit... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 18275 ; free virtual = 44744 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 18271 ; free virtual = 44740 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 18269 ; free virtual = 44740 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 18272 ; free virtual = 44742 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 18279 ; free virtual = 44749 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1987.242 ; gain = 515.531 ; free physical = 18289 ; free virtual = 44759 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1987.242 ; gain = 581.562 ; free physical = 18290 ; free virtual = 44760 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading route data... Processing options... Creating bitmap... Loading site data... Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:16] Creating bitstream... WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 18372 ; free virtual = 44843 --------------------------------------------------------------------------------- Creating bitstream... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:04:39 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2453.867 ; gain = 341.105 ; free physical = 18333 ; free virtual = 44810 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:04:39 2019... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.945 ; gain = 132.332 ; free physical = 18339 ; free virtual = 44810 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1235.973 ; gain = 140.359 ; free physical = 18338 ; free virtual = 44809 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Loading site data... touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 Loading route data... Processing options... Creating bitmap... Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.176 ; gain = 44.668 ; free physical = 19062 ; free virtual = 45533 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.164 ; gain = 51.656 ; free physical = 19034 ; free virtual = 45505 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.164 ; gain = 51.656 ; free physical = 19034 ; free virtual = 45505 Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2085.469 ; gain = 62.961 ; free physical = 18890 ; free virtual = 45362 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 19138 ; free virtual = 45613 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 19111 ; free virtual = 45586 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 19104 ; free virtual = 45579 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 19099 ; free virtual = 45574 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 19094 ; free virtual = 45569 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 19089 ; free virtual = 45564 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.469 ; gain = 65.961 ; free physical = 19012 ; free virtual = 45487 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2090.469 ; gain = 67.961 ; free physical = 19008 ; free virtual = 45483 Phase 9 Depositing Routes Writing bitstream ./design.bit... Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.469 ; gain = 68.961 ; free physical = 19065 ; free virtual = 45541 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2091.469 ; gain = 68.961 ; free physical = 19096 ; free virtual = 45572 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2130.258 ; gain = 139.766 ; free physical = 19094 ; free virtual = 45570 Writing placer database... INFO: [Timing 38-35] Done setting XDC timing constraints. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2130.258 ; gain = 0.000 ; free physical = 19293 ; free virtual = 45775 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 1267.965 ; gain = 172.352 ; free physical = 19366 ; free virtual = 45846 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 19365 ; free virtual = 45845 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1 Build RT Design | Checksum: 130471fa6 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2136.078 ; gain = 51.668 ; free physical = 19295 ; free virtual = 45775 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 19285 ; free virtual = 45765 Phase 1.3 Build Placer Netlist Model Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 130471fa6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2146.066 ; gain = 61.656 ; free physical = 19218 ; free virtual = 45697 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 130471fa6 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2146.066 ; gain = 61.656 ; free physical = 19216 ; free virtual = 45695 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:04:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 2532.367 ; gain = 339.105 ; free physical = 19166 ; free virtual = 45645 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:04:46 2019... Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:43 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 19327 ; free virtual = 45810 Phase 3 Initial Routing INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_007/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:04:46 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 2530.902 ; gain = 337.105 ; free physical = 20277 ; free virtual = 46760 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:04:46 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Vivado 12-1842] Bitgen Completed Successfully. Number of Nodes with overlaps = 0 INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 3 Initial Routing | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 20604 ; free virtual = 47086 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 21247 ; free virtual = 47730 touch build/specimen_008/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 Phase 4 Rip-up And Reroute | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 21522 ; free virtual = 48005 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 21547 ; free virtual = 48030 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Phase 6.1 Hold Fix Iter | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 21540 ; free virtual = 48023 DONE Phase 6 Post Hold Fix | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 21538 ; free virtual = 48022 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 21452 ; free virtual = 47935 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:44 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 21435 ; free virtual = 47918 Phase 9 Depositing Routes touch build/specimen_007/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 9 Depositing Routes | Checksum: 10f1fcbd8 Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 21399 ; free virtual = 47882 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2179.996 ; gain = 95.586 ; free physical = 21444 ; free virtual = 47927 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:49 . Memory (MB): peak = 2218.785 ; gain = 166.391 ; free physical = 21444 ; free virtual = 47927 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:06 . Memory (MB): peak = 1476.844 ; gain = 393.953 ; free physical = 21466 ; free virtual = 47949 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Writing placer database... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 21560 ; free virtual = 48049 --------------------------------------------------------------------------------- Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 21555 ; free virtual = 48044 Phase 1.4 Constrain Clocks/Macros Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1344.551 ; gain = 248.938 ; free physical = 21520 ; free virtual = 48011 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 21506 ; free virtual = 47997 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.156 ; gain = 455.203 ; free physical = 21473 ; free virtual = 47965 Phase 2 Global Placement ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:25 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 21431 ; free virtual = 47926 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 21391 ; free virtual = 47893 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 21385 ; free virtual = 47888 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 1 Placer Initialization INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.1 Placer Initialization Netlist Sorting --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 21369 ; free virtual = 47872 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 21368 ; free virtual = 47872 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1553.875 ; gain = 0.000 ; free physical = 21368 ; free virtual = 47872 --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 21368 ; free virtual = 47872 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 21368 ; free virtual = 47872 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 21367 ; free virtual = 47872 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:04:50 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.574 ; gain = 269.961 ; free physical = 21374 ; free virtual = 47878 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 1365.582 ; gain = 269.961 ; free physical = 21376 ; free virtual = 47880 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 2532.363 ; gain = 338.105 ; free physical = 21384 ; free virtual = 47889 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:04:50 2019... INFO: [Project 1-571] Translating synthesized netlist Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.48 . Memory (MB): peak = 1553.875 ; gain = 0.000 ; free physical = 21358 ; free virtual = 47863 Writing XDEF routing. Bitstream size: 4243411 bytes Writing XDEF routing logical nets. Writing XDEF routing special nets. Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5195 Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2218.785 ; gain = 0.000 ; free physical = 22400 ; free virtual = 48911 touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 22299 ; free virtual = 48812 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 22292 ; free virtual = 48806 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 22341 ; free virtual = 48827 Phase 3.3 Area Swap Optimization INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 22298 ; free virtual = 48784 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 22273 ; free virtual = 48760 Phase 3.5 Small Shape Detail Placement Phase 1 Build RT Design | Checksum: a1f8442e Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2067.953 ; gain = 41.668 ; free physical = 22299 ; free virtual = 48785 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Running DRC as a precondition to command write_bitstream Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: a1f8442e Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 22224 ; free virtual = 48711 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: a1f8442e Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2074.941 ; gain = 48.656 ; free physical = 22222 ; free virtual = 48708 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 10276a5af Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2087.371 ; gain = 61.086 ; free physical = 22181 ; free virtual = 48668 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 22066 ; free virtual = 48553 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 22133 ; free virtual = 48620 Phase 4 Rip-up And Reroute | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 22128 ; free virtual = 48615 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 22127 ; free virtual = 48614 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 22124 ; free virtual = 48610 Phase 6 Post Hold Fix | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 22119 ; free virtual = 48606 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2089.371 ; gain = 63.086 ; free physical = 22094 ; free virtual = 48581 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.371 ; gain = 65.086 ; free physical = 22094 ; free virtual = 48581 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 10276a5af Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.371 ; gain = 65.086 ; free physical = 22092 ; free virtual = 48578 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.371 ; gain = 65.086 ; free physical = 22130 ; free virtual = 48617 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 2130.160 ; gain = 135.891 ; free physical = 22129 ; free virtual = 48616 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 22099 ; free virtual = 48588 Phase 3.6 Re-assign LUT pins Write XDEF Complete: Time (s): cpu = 00:00:00.95 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2130.160 ; gain = 0.000 ; free physical = 22082 ; free virtual = 48572 Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 22081 ; free virtual = 48572 Phase 3.7 Pipeline Register Optimization INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 22071 ; free virtual = 48558 Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 22010 ; free virtual = 48500 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 21979 ; free virtual = 48471 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 21940 ; free virtual = 48434 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 21880 ; free virtual = 48377 Phase 4.4 Final Placement Cleanup Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 21846 ; free virtual = 48344 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 21812 ; free virtual = 48313 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:31 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 551.250 ; free physical = 21808 ; free virtual = 48311 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 21807 ; free virtual = 48310 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Creating bitstream... INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 1467.246 ; gain = 384.359 ; free physical = 21361 ; free virtual = 47911 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 21186 ; free virtual = 47753 --------------------------------------------------------------------------------- Loading data files... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1538.277 ; gain = 0.000 ; free physical = 21379 ; free virtual = 47957 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1538.277 ; gain = 0.000 ; free physical = 21331 ; free virtual = 47908 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading data files... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:05:07 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2464.434 ; gain = 334.176 ; free physical = 20861 ; free virtual = 47440 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:05:07 2019... INFO: Launching helper process for spawning children vivado processes WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:16] INFO: Helper process launched with PID 5630 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:7] touch build/specimen_011/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_012 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/top.v:2] INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 21513 ; free virtual = 48094 --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.363 ; gain = 0.000 ; free physical = 21466 ; free virtual = 48048 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 21467 ; free virtual = 48048 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 21469 ; free virtual = 48051 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Helper process launched with PID 5746 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 2052.406 ; gain = 498.531 ; free physical = 21216 ; free virtual = 47799 Phase 1.3 Build Placer Netlist Model INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5781 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 21133 ; free virtual = 47716 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Loading site data... Loading route data... Processing options... Creating bitmap... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 5821 Loading site data... Loading route data... Processing options... Creating bitmap... Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.406 ; gain = 498.531 ; free physical = 20693 ; free virtual = 47279 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2052.406 ; gain = 498.531 ; free physical = 20687 ; free virtual = 47274 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 20681 ; free virtual = 47268 --------------------------------------------------------------------------------- Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.406 ; gain = 498.531 ; free physical = 20681 ; free virtual = 47267 Phase 2 Final Placement Cleanup Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2062.926 ; gain = 43.668 ; free physical = 20677 ; free virtual = 47264 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.914 ; gain = 50.656 ; free physical = 20636 ; free virtual = 47223 Phase 2.2 Pre Route Cleanup Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2069.914 ; gain = 50.656 ; free physical = 20636 ; free virtual = 47223 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.406 ; gain = 498.531 ; free physical = 20630 ; free virtual = 47217 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.406 ; gain = 498.531 ; free physical = 20674 ; free virtual = 47261 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.406 ; gain = 575.562 ; free physical = 20667 ; free virtual = 47254 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:39 ; elapsed = 00:00:41 . Memory (MB): peak = 2079.969 ; gain = 60.711 ; free physical = 20674 ; free virtual = 47261 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 20651 ; free virtual = 47239 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 20625 ; free virtual = 47213 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 20623 ; free virtual = 47210 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 20621 ; free virtual = 47209 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 20620 ; free virtual = 47208 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 20620 ; free virtual = 47208 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 20620 ; free virtual = 47208 Phase 7 Route finalize --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:29 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 20610 ; free virtual = 47198 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2082.969 ; gain = 63.711 ; free physical = 20582 ; free virtual = 47170 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2084.969 ; gain = 65.711 ; free physical = 20581 ; free virtual = 47168 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2084.969 ; gain = 65.711 ; free physical = 20577 ; free virtual = 47165 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2084.969 ; gain = 65.711 ; free physical = 20606 ; free virtual = 47194 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2123.758 ; gain = 136.516 ; free physical = 20600 ; free virtual = 47188 Writing placer database... Writing XDEF routing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20575 ; free virtual = 47163 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Writing XDEF routing logical nets. Writing XDEF routing special nets. --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.41 . Memory (MB): peak = 2123.758 ; gain = 0.000 ; free physical = 20572 ; free virtual = 47163 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 20562 ; free virtual = 47151 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 20528 ; free virtual = 47118 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 20522 ; free virtual = 47112 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 20564 ; free virtual = 47154 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20573 ; free virtual = 47163 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20599 ; free virtual = 47189 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20603 ; free virtual = 47193 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20605 ; free virtual = 47194 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20602 ; free virtual = 47192 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20605 ; free virtual = 47194 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20605 ; free virtual = 47194 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 20601 ; free virtual = 47191 Starting Routing Task Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 20597 ; free virtual = 47188 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 20563 ; free virtual = 47153 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:12 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 20555 ; free virtual = 47146 --------------------------------------------------------------------------------- Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:1575] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/top.v:2] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/top.v:2] INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20201 ; free virtual = 46793 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20198 ; free virtual = 46790 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20185 ; free virtual = 46778 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20179 ; free virtual = 46772 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20154 ; free virtual = 46747 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20150 ; free virtual = 46743 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20149 ; free virtual = 46741 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20108 ; free virtual = 46701 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 20034 ; free virtual = 46626 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. Writing bitstream ./design.bit... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.766 ; gain = 0.000 ; free physical = 19920 ; free virtual = 46518 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Creating bitstream... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20060 ; free virtual = 46658 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 20050 ; free virtual = 46648 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20048 ; free virtual = 46646 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 20031 ; free virtual = 46630 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.480 ; gain = 465.203 ; free physical = 19947 ; free virtual = 46546 Phase 1.3 Build Placer Netlist Model Writing bitstream ./design.bit... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 19983 ; free virtual = 46586 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 19973 ; free virtual = 46577 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 19972 ; free virtual = 46576 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:05:30 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:35 . Memory (MB): peak = 2468.266 ; gain = 338.105 ; free physical = 19977 ; free virtual = 46580 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:05:31 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20859 ; free virtual = 47464 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20859 ; free virtual = 47463 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20857 ; free virtual = 47462 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20857 ; free virtual = 47461 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20856 ; free virtual = 47460 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20856 ; free virtual = 47460 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20856 ; free virtual = 47460 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 20854 ; free virtual = 47459 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:25 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 20854 ; free virtual = 47459 INFO: [Project 1-571] Translating synthesized netlist touch build/specimen_010/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.480 ; gain = 465.203 ; free physical = 20828 ; free virtual = 47434 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.480 ; gain = 465.203 ; free physical = 20774 ; free virtual = 47380 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 2003.480 ; gain = 465.203 ; free physical = 20738 ; free virtual = 47344 Phase 2 Global Placement INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 20754 ; free virtual = 47361 --------------------------------------------------------------------------------- 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:43 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 20761 ; free virtual = 47367 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 20728 ; free virtual = 47335 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20711 ; free virtual = 47318 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_008/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:05:33 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 20693 ; free virtual = 47300 --------------------------------------------------------------------------------- 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:03 ; elapsed = 00:00:41 . Memory (MB): peak = 2607.906 ; gain = 389.121 ; free physical = 20699 ; free virtual = 47306 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:05:33 2019... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 20687 ; free virtual = 47293 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 20726 ; free virtual = 47331 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 INFO: Launching helper process for spawning children vivado processes DONE INFO: Helper process launched with PID 6854 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21812 ; free virtual = 48419 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21815 ; free virtual = 48422 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21814 ; free virtual = 48421 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21814 ; free virtual = 48421 --------------------------------------------------------------------------------- WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21813 ; free virtual = 48420 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21813 ; free virtual = 48420 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21813 ; free virtual = 48419 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21812 ; free virtual = 48419 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 21815 ; free virtual = 48421 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-571] Translating synthesized netlist Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1546.953 ; gain = 0.000 ; free physical = 21763 ; free virtual = 48370 touch build/specimen_008/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_013 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1546.953 ; gain = 0.000 ; free physical = 21721 ; free virtual = 48329 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21712 ; free virtual = 48319 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21711 ; free virtual = 48318 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21731 ; free virtual = 48339 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21731 ; free virtual = 48339 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21730 ; free virtual = 48338 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21729 ; free virtual = 48336 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21728 ; free virtual = 48336 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21726 ; free virtual = 48334 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 21727 ; free virtual = 48334 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 21616 ; free virtual = 48225 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21608 ; free virtual = 48217 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1303.688 ; gain = 208.242 ; free physical = 21607 ; free virtual = 48216 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21609 ; free virtual = 48217 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-570] Preparing netlist for logic optimization 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:29 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 21685 ; free virtual = 48295 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 INFO: [DRC 23-27] Running DRC with 8 threads Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21684 ; free virtual = 48294 Phase 3.2 Commit Most Macros & LUTRAMs report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21600 ; free virtual = 48210 Phase 3.3 Area Swap Optimization --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21564 ; free virtual = 48174 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21564 ; free virtual = 48174 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21561 ; free virtual = 48171 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21560 ; free virtual = 48169 --------------------------------------------------------------------------------- Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21558 ; free virtual = 48167 Phase 3.4 Pipeline Register Optimization --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21556 ; free virtual = 48166 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21556 ; free virtual = 48165 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21553 ; free virtual = 48163 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.664 ; gain = 216.219 ; free physical = 21550 ; free virtual = 48160 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.672 ; gain = 216.219 ; free physical = 21553 ; free virtual = 48163 INFO: [Project 1-571] Translating synthesized netlist Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21538 ; free virtual = 48148 Phase 3.5 Small Shape Detail Placement Loading site data... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 21516 ; free virtual = 48127 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1463.715 ; gain = 0.000 ; free physical = 21516 ; free virtual = 48126 Loading route data... Processing options... Creating bitmap... INFO: [Project 1-570] Preparing netlist for logic optimization Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21348 ; free virtual = 47959 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21293 ; free virtual = 47905 Phase 3.7 Pipeline Register Optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21269 ; free virtual = 47881 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 21296 ; free virtual = 47908 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks Phase 3 Detail Placement | Checksum: 181723f81 INFO: [DRC 23-27] Running DRC with 8 threads Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21290 ; free virtual = 47902 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21261 ; free virtual = 47873 Phase 4.2 Post Placement Cleanup INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 21281 ; free virtual = 47893 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21288 ; free virtual = 47901 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21265 ; free virtual = 47877 Phase 4.4 Final Placement Cleanup report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21244 ; free virtual = 47857 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 21231 ; free virtual = 47844 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 21230 ; free virtual = 47843 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21218 ; free virtual = 47831 Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.523 ; gain = 553.246 ; free physical = 21237 ; free virtual = 47851 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 2091.523 ; gain = 624.277 ; free physical = 21237 ; free virtual = 47850 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 21224 ; free virtual = 47837 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1463.719 ; gain = 0.000 ; free physical = 21224 ; free virtual = 47837 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2129.430 ; gain = 30.227 ; free physical = 21160 ; free virtual = 47773 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 21174 ; free virtual = 47788 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.418 ; gain = 37.215 ; free physical = 21144 ; free virtual = 47757 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2136.418 ; gain = 37.215 ; free physical = 21144 ; free virtual = 47757 Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 21118 ; free virtual = 47732 Phase 3 Initial Routing --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 21113 ; free virtual = 47726 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 21159 ; free virtual = 47773 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 21159 ; free virtual = 47773 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 21158 ; free virtual = 47772 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 21158 ; free virtual = 47772 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 21158 ; free virtual = 47772 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 21158 ; free virtual = 47772 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 21156 ; free virtual = 47771 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 21155 ; free virtual = 47770 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 21156 ; free virtual = 47770 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.473 ; gain = 55.270 ; free physical = 21191 ; free virtual = 47805 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2193.262 ; gain = 94.059 ; free physical = 21190 ; free virtual = 47805 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 21187 ; free virtual = 47802 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 21187 ; free virtual = 47802 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Writing placer database... INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:120] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 20977 ; free virtual = 47606 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 21043 ; free virtual = 47673 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 21042 ; free virtual = 47673 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 21037 ; free virtual = 47668 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2193.262 ; gain = 0.000 ; free physical = 20951 ; free virtual = 47593 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:05:51 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 2461.863 ; gain = 338.105 ; free physical = 21046 ; free virtual = 47670 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:05:51 2019... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_009/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_010 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading data files... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 21369 ; free virtual = 47995 --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.926 ; gain = 210.484 ; free physical = 21346 ; free virtual = 47972 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 21325 ; free virtual = 47951 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7315 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 21240 ; free virtual = 47867 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 21083 ; free virtual = 47710 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 21080 ; free virtual = 47707 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 21069 ; free virtual = 47696 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 21064 ; free virtual = 47691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 21061 ; free virtual = 47688 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 21058 ; free virtual = 47685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 21054 ; free virtual = 47682 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.902 ; gain = 218.461 ; free physical = 21045 ; free virtual = 47672 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 21043 ; free virtual = 47671 INFO: [Project 1-571] Translating synthesized netlist INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 20879 ; free virtual = 47507 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:23 . Memory (MB): peak = 2003.156 ; gain = 456.203 ; free physical = 20871 ; free virtual = 47499 Phase 1.3 Build Placer Netlist Model INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 20836 ; free virtual = 47464 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 20816 ; free virtual = 47444 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 20815 ; free virtual = 47443 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 20814 ; free virtual = 47442 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 20813 ; free virtual = 47441 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 468.531 ; free physical = 20813 ; free virtual = 47441 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 20813 ; free virtual = 47441 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 7416 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 19959 ; free virtual = 46590 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 19950 ; free virtual = 46580 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 456.203 ; free physical = 19918 ; free virtual = 46548 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 456.203 ; free physical = 19903 ; free virtual = 46534 Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.156 ; gain = 456.203 ; free physical = 19868 ; free virtual = 46499 Phase 2 Global Placement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1406.926 ; gain = 324.039 ; free physical = 19886 ; free virtual = 46516 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 19849 ; free virtual = 46480 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 19829 ; free virtual = 46460 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 19827 ; free virtual = 46458 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 19825 ; free virtual = 46456 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 19824 ; free virtual = 46455 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 19820 ; free virtual = 46452 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 19820 ; free virtual = 46451 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 19781 ; free virtual = 46413 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 19767 ; free virtual = 46398 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 19765 ; free virtual = 46396 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 19763 ; free virtual = 46394 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 19761 ; free virtual = 46392 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 468.531 ; free physical = 19760 ; free virtual = 46391 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 19760 ; free virtual = 46391 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.207 ; gain = 0.000 ; free physical = 19600 ; free virtual = 46231 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 19574 ; free virtual = 46206 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1472.957 ; gain = 0.000 ; free physical = 19577 ; free virtual = 46209 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 19522 ; free virtual = 46156 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 19522 ; free virtual = 46155 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 19522 ; free virtual = 46155 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 19522 ; free virtual = 46155 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 19522 ; free virtual = 46155 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1932.250 ; gain = 469.531 ; free physical = 19523 ; free virtual = 46157 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.250 ; gain = 534.562 ; free physical = 19523 ; free virtual = 46157 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Phase 1 Build RT Design | Checksum: 10072c28e Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2135.090 ; gain = 50.668 ; free physical = 19486 ; free virtual = 46120 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 19479 ; free virtual = 46113 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 10072c28e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2144.078 ; gain = 59.656 ; free physical = 19390 ; free virtual = 46025 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 10072c28e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2144.078 ; gain = 59.656 ; free physical = 19376 ; free virtual = 46011 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19341 ; free virtual = 45976 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19355 ; free virtual = 45990 Phase 3.2 Commit Most Macros & LUTRAMs Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1a3bb806c Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.008 ; gain = 95.586 ; free physical = 19239 ; free virtual = 45875 Phase 3 Initial Routing Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19166 ; free virtual = 45802 Phase 3.3 Area Swap Optimization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Number of Nodes with overlaps = Parameter IS_RSTREGB_INVERTED bound to: 1'b0 0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:893] Phase 3 Initial Routing | Checksum: 1a3bb806c Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.008 ; gain = 95.586 ; free physical = 19108 ; free virtual = 45744 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3401] Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4563] Phase 3.3 Area Swap Optimization | Checksum: 23216312d WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4646] Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19179 ; free virtual = 45815 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4812] Phase 3.4 Pipeline Register Optimization WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5891] Phase 4.1 Global Iteration 0 | Checksum: 1a3bb806c Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.008 ; gain = 95.586 ; free physical = 19178 ; free virtual = 45813 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7219] Phase 4 Rip-up And Reroute | Checksum: 1a3bb806c Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.008 ; gain = 95.586 ; free physical = 19176 ; free virtual = 45812 WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7302] Phase 5 Delay and Skew Optimization WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 5 Delay and Skew Optimization | Checksum: 1a3bb806c Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.008 ; gain = 95.586 ; free physical = 19172 ; free virtual = 45808 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1a3bb806c Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.008 ; gain = 95.586 ; free physical = 19166 ; free virtual = 45802 Phase 6 Post Hold Fix | Checksum: 1a3bb806c Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2180.008 ; gain = 95.586 ; free physical = 19165 ; free virtual = 45801 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19158 ; free virtual = 45794 Phase 3.5 Small Shape Detail Placement Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.008 ; gain = 95.586 ; free physical = 19156 ; free virtual = 45792 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.008 ; gain = 95.586 ; free physical = 19154 ; free virtual = 45790 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 19154 ; free virtual = 45790 --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/top.v:2] Creating bitstream... Phase 9 Depositing Routes | Checksum: 1a3bb806c Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.008 ; gain = 95.586 ; free physical = 19173 ; free virtual = 45811 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2180.008 ; gain = 95.586 ; free physical = 19212 ; free virtual = 45851 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2218.797 ; gain = 166.391 ; free physical = 19210 ; free virtual = 45851 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 19194 ; free virtual = 45832 --------------------------------------------------------------------------------- Writing placer database... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 19178 ; free virtual = 45820 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 19178 ; free virtual = 45819 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 19120 ; free virtual = 45765 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19104 ; free virtual = 45749 Phase 3.6 Re-assign LUT pins INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:64] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:155] Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19076 ; free virtual = 45723 WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:176] Phase 3.7 Pipeline Register Optimization WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/top.v:2] Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19070 ; free virtual = 45717 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 19092 ; free virtual = 45741 --------------------------------------------------------------------------------- Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19091 ; free virtual = 45742 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 19087 ; free virtual = 45738 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 19087 ; free virtual = 45739 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19082 ; free virtual = 45735 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 19081 ; free virtual = 45734 --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19070 ; free virtual = 45724 Phase 4.3 Placer Reporting Writing bitstream ./design.bit... Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19038 ; free virtual = 45695 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19054 ; free virtual = 45716 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19214 ; free virtual = 45877 INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 552.250 ; free physical = 19238 ; free virtual = 45903 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 19235 ; free virtual = 45900 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2218.797 ; gain = 0.000 ; free physical = 19121 ; free virtual = 45793 WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2218.797 ; gain = 0.000 ; free physical = 19050 ; free virtual = 45698 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:06:16 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 2532.367 ; gain = 339.105 ; free physical = 18902 ; free virtual = 45551 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:06:16 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_011 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 8438 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 19755 ; free virtual = 46405 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1311.688 ; gain = 216.238 ; free physical = 19763 ; free virtual = 46413 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 19754 ; free virtual = 46404 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:22 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 19763 ; free virtual = 46414 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 19756 ; free virtual = 46408 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 19756 ; free virtual = 46408 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 19753 ; free virtual = 46405 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 19753 ; free virtual = 46405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 19753 ; free virtual = 46405 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 19752 ; free virtual = 46403 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 19751 ; free virtual = 46403 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 19751 ; free virtual = 46402 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.672 ; gain = 225.223 ; free physical = 19750 ; free virtual = 46401 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:25 . Memory (MB): peak = 1320.680 ; gain = 225.223 ; free physical = 19749 ; free virtual = 46401 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19749 ; free virtual = 46401 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19705 ; free virtual = 46358 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19705 ; free virtual = 46358 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19703 ; free virtual = 46356 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19704 ; free virtual = 46357 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19704 ; free virtual = 46357 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19704 ; free virtual = 46357 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19704 ; free virtual = 46357 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 19702 ; free virtual = 46355 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 19703 ; free virtual = 46357 INFO: [Project 1-571] Translating synthesized netlist WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.445 ; gain = 0.000 ; free physical = 19098 ; free virtual = 45755 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 18982 ; free virtual = 45639 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 18972 ; free virtual = 45630 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 18972 ; free virtual = 45630 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 18976 ; free virtual = 45634 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 18967 ; free virtual = 45624 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.488 ; gain = 518.531 ; free physical = 18935 ; free virtual = 45593 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1991.488 ; gain = 584.562 ; free physical = 18926 ; free virtual = 45584 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.445 ; gain = 54.992 ; free physical = 18887 ; free virtual = 45545 --------------------------------------------------------------------------------- Loading data files... Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2129.285 ; gain = 37.762 ; free physical = 18863 ; free virtual = 45521 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2135.273 ; gain = 43.750 ; free physical = 18822 ; free virtual = 45481 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2135.273 ; gain = 43.750 ; free physical = 18822 ; free virtual = 45481 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:33 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 18823 ; free virtual = 45482 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.328 ; gain = 62.805 ; free physical = 18842 ; free virtual = 45501 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 18845 ; free virtual = 45504 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.328 ; gain = 62.805 ; free physical = 18815 ; free virtual = 45474 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.328 ; gain = 62.805 ; free physical = 18814 ; free virtual = 45473 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.328 ; gain = 62.805 ; free physical = 18814 ; free virtual = 45473 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.328 ; gain = 62.805 ; free physical = 18814 ; free virtual = 45473 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.328 ; gain = 62.805 ; free physical = 18813 ; free virtual = 45472 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.328 ; gain = 62.805 ; free physical = 18813 ; free virtual = 45472 Starting Routing Task Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.328 ; gain = 62.805 ; free physical = 18796 ; free virtual = 45455 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.328 ; gain = 62.805 ; free physical = 18794 ; free virtual = 45453 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.328 ; gain = 62.805 ; free physical = 18795 ; free virtual = 45455 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2154.328 ; gain = 62.805 ; free physical = 18828 ; free virtual = 45487 Routing Is Done. Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2193.117 ; gain = 101.594 ; free physical = 18826 ; free virtual = 45486 Phase 1 Build RT Design Writing placer database... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/top.v:2] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 18762 ; free virtual = 45427 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1481.742 ; gain = 0.000 ; free physical = 18761 ; free virtual = 45426 Starting Placer Task Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1481.742 ; gain = 0.000 ; free physical = 18769 ; free virtual = 45435 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 18769 ; free virtual = 45435 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 18764 ; free virtual = 45435 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1194.953 ; gain = 99.500 ; free physical = 18764 ; free virtual = 45431 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 18764 ; free virtual = 45431 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1202.980 ; gain = 107.527 ; free physical = 18761 ; free virtual = 45428 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.117 ; gain = 0.000 ; free physical = 18567 ; free virtual = 45252 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.934 ; gain = 210.480 ; free physical = 18100 ; free virtual = 44768 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.934 ; gain = 210.480 ; free physical = 18094 ; free virtual = 44762 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 18075 ; free virtual = 44743 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 18022 ; free virtual = 44692 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 18023 ; free virtual = 44693 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 18022 ; free virtual = 44692 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 18022 ; free virtual = 44692 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 18022 ; free virtual = 44692 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 18022 ; free virtual = 44691 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 18022 ; free virtual = 44691 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.910 ; gain = 218.457 ; free physical = 18021 ; free virtual = 44690 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1313.918 ; gain = 218.457 ; free physical = 18022 ; free virtual = 44691 INFO: [Project 1-571] Translating synthesized netlist INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 8784 INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1 Build RT Design | Checksum: 147c14821 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2056.930 ; gain = 92.668 ; free physical = 17817 ; free virtual = 44490 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 147c14821 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 17784 ; free virtual = 44457 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 147c14821 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2061.918 ; gain = 97.656 ; free physical = 17783 ; free virtual = 44456 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 128d436ff Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.973 ; gain = 103.711 ; free physical = 17766 ; free virtual = 44439 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 17758 ; free virtual = 44431 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 17758 ; free virtual = 44431 Phase 4 Rip-up And Reroute | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 17758 ; free virtual = 44431 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 17758 ; free virtual = 44431 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 17758 ; free virtual = 44431 Phase 6 Post Hold Fix | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 17758 ; free virtual = 44431 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2068.973 ; gain = 104.711 ; free physical = 17744 ; free virtual = 44418 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 17742 ; free virtual = 44416 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 128d436ff Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 17743 ; free virtual = 44417 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2071.973 ; gain = 107.711 ; free physical = 17776 ; free virtual = 44450 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2110.762 ; gain = 178.516 ; free physical = 17776 ; free virtual = 44450 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2110.762 ; gain = 0.000 ; free physical = 17772 ; free virtual = 44447 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 147c036e4 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2055.934 ; gain = 91.668 ; free physical = 17614 ; free virtual = 44290 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 147c036e4 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2060.922 ; gain = 96.656 ; free physical = 17596 ; free virtual = 44271 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 147c036e4 Time (s): cpu = 00:00:39 ; elapsed = 00:00:45 . Memory (MB): peak = 2060.922 ; gain = 96.656 ; free physical = 17596 ; free virtual = 44271 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 161e7cd46 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17571 ; free virtual = 44247 Phase 3 Initial Routing 14 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1404.934 ; gain = 322.039 ; free physical = 17573 ; free virtual = 44249 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17578 ; free virtual = 44255 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17571 ; free virtual = 44248 Phase 4 Rip-up And Reroute | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17571 ; free virtual = 44247 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17571 ; free virtual = 44247 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17570 ; free virtual = 44246 Phase 6 Post Hold Fix | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17569 ; free virtual = 44246 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17510 ; free virtual = 44187 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 17507 ; free virtual = 44183 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 161e7cd46 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 17508 ; free virtual = 44184 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 17541 ; free virtual = 44217 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2109.766 ; gain = 177.516 ; free physical = 17540 ; free virtual = 44216 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2109.766 ; gain = 0.000 ; free physical = 17543 ; free virtual = 44222 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.965 ; gain = 0.000 ; free physical = 17226 ; free virtual = 43908 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1471.965 ; gain = 0.000 ; free physical = 17258 ; free virtual = 43940 Running DRC as a precondition to command write_bitstream INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1 Build RT Design | Checksum: 97328c80 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2057.934 ; gain = 93.668 ; free physical = 17465 ; free virtual = 44147 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 97328c80 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2063.922 ; gain = 99.656 ; free physical = 17384 ; free virtual = 44066 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 97328c80 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2063.922 ; gain = 99.656 ; free physical = 17383 ; free virtual = 44065 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1 Build RT Design | Checksum: eb6f845d Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2055.934 ; gain = 91.668 ; free physical = 17330 ; free virtual = 44012 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1902.449 ; gain = 0.000 ; free physical = 17326 ; free virtual = 44009 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: eb6f845d Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.922 ; gain = 96.656 ; free physical = 17217 ; free virtual = 43899 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: eb6f845d Time (s): cpu = 00:00:39 ; elapsed = 00:00:46 . Memory (MB): peak = 2060.922 ; gain = 96.656 ; free physical = 17215 ; free virtual = 43898 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 17194 ; free virtual = 43877 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 17082 ; free virtual = 43764 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 6c93b630 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17106 ; free virtual = 43788 Phase 3 Initial Routing Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 17110 ; free virtual = 43792 Phase 1.3 Build Placer Netlist Model Phase 4.1 Global Iteration 0 | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 17114 ; free virtual = 43796 Phase 4 Rip-up And Reroute | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 17114 ; free virtual = 43797 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 17114 ; free virtual = 43797 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 17115 ; free virtual = 43797 Phase 6 Post Hold Fix | Checksum: 1088853dc Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 2069.977 ; gain = 105.711 ; free physical = 17115 ; free virtual = 43797 INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Loading site data... Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 17125 ; free virtual = 43808 Phase 1.4 Constrain Clocks/Macros Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1088853dc Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 17122 ; free virtual = 43805 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1088853dc Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.977 ; gain = 109.711 ; free physical = 17122 ; free virtual = 43805 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 1088853dc Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.977 ; gain = 109.711 ; free physical = 17121 ; free virtual = 43804 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2073.977 ; gain = 109.711 ; free physical = 17161 ; free virtual = 43844 Routing Is Done. Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 17161 ; free virtual = 43844 Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1150.438 ; gain = 54.992 ; free physical = 17121 ; free virtual = 43803 --------------------------------------------------------------------------------- 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:51 . Memory (MB): peak = 2112.766 ; gain = 180.516 ; free physical = 17166 ; free virtual = 43848 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6c93b630 Time (s): cpu = 00:00:40 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17179 ; free virtual = 43862 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 17186 ; free virtual = 43868 Phase 2 Final Placement Cleanup INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17185 ; free virtual = 43868 Phase 4 Rip-up And Reroute | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17185 ; free virtual = 43868 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17185 ; free virtual = 43868 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17185 ; free virtual = 43868 Phase 6 Post Hold Fix | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17184 ; free virtual = 43867 Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 17184 ; free virtual = 43867 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 7 Route finalize Writing placer database... Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1990.492 ; gain = 517.531 ; free physical = 17188 ; free virtual = 43871 Writing XDEF routing. 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1990.492 ; gain = 583.562 ; free physical = 17187 ; free virtual = 43871 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2112.766 ; gain = 0.000 ; free physical = 17186 ; free virtual = 43871 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 17186 ; free virtual = 43870 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2067.977 ; gain = 103.711 ; free physical = 17178 ; free virtual = 43862 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 17176 ; free virtual = 43861 Phase 9 Depositing Routes INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 9 Depositing Routes | Checksum: 6c93b630 Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 17174 ; free virtual = 43857 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2070.977 ; gain = 106.711 ; free physical = 17201 ; free virtual = 43884 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2109.766 ; gain = 177.516 ; free physical = 17199 ; free virtual = 43883 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing placer database... Loading route data... Processing options... Writing XDEF routing. Creating bitmap... Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2109.766 ; gain = 0.000 ; free physical = 17155 ; free virtual = 43840 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 17124 ; free virtual = 43808 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 17083 ; free virtual = 43767 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 17067 ; free virtual = 43751 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 17051 ; free virtual = 43735 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 17021 ; free virtual = 43705 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.273 ; gain = 512.531 ; free physical = 17010 ; free virtual = 43695 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:26 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 17008 ; free virtual = 43692 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Running DRC as a precondition to command write_bitstream INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:328] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 17010 ; free virtual = 43696 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.945 ; gain = 99.500 ; free physical = 16970 ; free virtual = 43656 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 16974 ; free virtual = 43660 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_009/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:06:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Starting Routing Task INFO: [Device 21-403] Loading part xc7z020clg400-1 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:42 . Memory (MB): peak = 2606.957 ; gain = 388.160 ; free physical = 16978 ; free virtual = 43664 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:06:56 2019... INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.973 ; gain = 107.527 ; free physical = 16975 ; free virtual = 43660 --------------------------------------------------------------------------------- Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. touch build/specimen_009/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_010 Loading data files... Writing bitstream ./design.bit... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2129.961 ; gain = 30.758 ; free physical = 17911 ; free virtual = 44609 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Loading data files... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.949 ; gain = 36.746 ; free physical = 17830 ; free virtual = 44528 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:45 . Memory (MB): peak = 2135.949 ; gain = 36.746 ; free physical = 17827 ; free virtual = 44525 Loading data files... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 17778 ; free virtual = 44477 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 17748 ; free virtual = 44447 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 17743 ; free virtual = 44443 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 17743 ; free virtual = 44443 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 17743 ; free virtual = 44442 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 17743 ; free virtual = 44442 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 17743 ; free virtual = 44442 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 17716 ; free virtual = 44415 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 17715 ; free virtual = 44414 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 17712 ; free virtual = 44411 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2155.004 ; gain = 55.801 ; free physical = 17747 ; free virtual = 44446 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 2193.793 ; gain = 94.590 ; free physical = 17747 ; free virtual = 44446 Writing placer database... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:07:03 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2531.223 ; gain = 338.105 ; free physical = 17373 ; free virtual = 44085 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:07:03 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_011 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 18200 ; free virtual = 44920 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1306.684 ; gain = 211.238 ; free physical = 18186 ; free virtual = 44908 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:23 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18182 ; free virtual = 44904 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing XDEF routing. Loading site data... Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 2193.793 ; gain = 0.000 ; free physical = 18162 ; free virtual = 44887 Loading route data... Processing options... Creating bitmap... INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2193.793 ; gain = 0.000 ; free physical = 18169 ; free virtual = 44878 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18164 ; free virtual = 44874 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18160 ; free virtual = 44870 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18163 ; free virtual = 44873 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18155 ; free virtual = 44864 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18154 ; free virtual = 44863 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18151 ; free virtual = 44861 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18150 ; free virtual = 44860 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.660 ; gain = 219.215 ; free physical = 18141 ; free virtual = 44850 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1314.668 ; gain = 219.215 ; free physical = 18139 ; free virtual = 44849 INFO: [Project 1-571] Translating synthesized netlist Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement Creating bitstream... INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading site data... INFO: [Project 1-570] Preparing netlist for logic optimization Loading route data... Processing options... Creating bitmap... Creating bitstream... Loading site data... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... Loading site data... Loading route data... Processing options... Creating bitmap... Loading route data... Processing options... Creating bitmap... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Creating bitstream... Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Writing bitstream ./design.bit... 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1405.676 ; gain = 322.789 ; free physical = 17564 ; free virtual = 44284 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.453 ; gain = 0.000 ; free physical = 17564 ; free virtual = 44284 INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.496 ; gain = 514.531 ; free physical = 17679 ; free virtual = 44402 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.496 ; gain = 514.531 ; free physical = 17710 ; free virtual = 44432 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.496 ; gain = 514.531 ; free physical = 17724 ; free virtual = 44447 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.496 ; gain = 514.531 ; free physical = 17777 ; free virtual = 44500 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.496 ; gain = 514.531 ; free physical = 17822 ; free virtual = 44544 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1986.496 ; gain = 514.531 ; free physical = 17845 ; free virtual = 44568 25 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 1986.496 ; gain = 581.562 ; free physical = 17847 ; free virtual = 44570 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Loading data files... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.707 ; gain = 0.000 ; free physical = 17843 ; free virtual = 44566 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1471.707 ; gain = 0.000 ; free physical = 17842 ; free virtual = 44566 Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2067.172 ; gain = 43.668 ; free physical = 17841 ; free virtual = 44564 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 17810 ; free virtual = 44533 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2073.160 ; gain = 49.656 ; free physical = 17810 ; free virtual = 44533 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:07:14 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2451.867 ; gain = 341.105 ; free physical = 17802 ; free virtual = 44526 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:07:14 2019... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 17877 ; free virtual = 44601 Phase 3 Initial Routing report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 18704 ; free virtual = 45428 touch build/specimen_010/OK Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 18695 ; free virtual = 45420 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 18693 ; free virtual = 45418 Phase 5 Delay and Skew Optimization Writing bitstream ./design.bit... Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 18690 ; free virtual = 45416 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 18689 ; free virtual = 45414 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:47 . Memory (MB): peak = 2084.465 ; gain = 60.961 ; free physical = 18697 ; free virtual = 45423 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2085.465 ; gain = 61.961 ; free physical = 18647 ; free virtual = 45378 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 18649 ; free virtual = 45381 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 18744 ; free virtual = 45476 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.465 ; gain = 64.961 ; free physical = 18795 ; free virtual = 45527 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2127.254 ; gain = 135.766 ; free physical = 18800 ; free virtual = 45532 Writing placer database... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.74 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2127.254 ; gain = 0.000 ; free physical = 19244 ; free virtual = 45979 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:07:17 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 2452.871 ; gain = 343.105 ; free physical = 19197 ; free virtual = 45937 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:07:17 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:07:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2455.871 ; gain = 343.105 ; free physical = 20033 ; free virtual = 46774 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:07:19 2019... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:07:19 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 2453.871 ; gain = 344.105 ; free physical = 20681 ; free virtual = 47423 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:07:19 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9753 Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 9844 Loading site data... --------------------------------------------------------------------------------- Loading route data... Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.559 ; gain = 81.648 ; free physical = 21226 ; free virtual = 47985 --------------------------------------------------------------------------------- Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:07:31 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 2532.398 ; gain = 338.605 ; free physical = 20972 ; free virtual = 47732 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:07:32 2019... INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.195 ; gain = 0.000 ; free physical = 20964 ; free virtual = 47723 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.238 ; gain = 514.531 ; free physical = 21839 ; free virtual = 48598 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.238 ; gain = 514.531 ; free physical = 21913 ; free virtual = 48673 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.238 ; gain = 514.531 ; free physical = 21913 ; free virtual = 48672 Bitstream size: 4243411 bytes Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.238 ; gain = 514.531 ; free physical = 21907 ; free virtual = 48667 Phase 2 Final Placement Cleanup Config size: 1060815 words Number of configuration frames: 9996 DONE Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.238 ; gain = 514.531 ; free physical = 21910 ; free virtual = 48670 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1986.238 ; gain = 514.531 ; free physical = 21877 ; free virtual = 48637 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.238 ; gain = 580.562 ; free physical = 21875 ; free virtual = 48635 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_012/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_013 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Creating bitstream... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2067.176 ; gain = 44.668 ; free physical = 21740 ; free virtual = 48505 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2074.164 ; gain = 51.656 ; free physical = 21702 ; free virtual = 48467 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2074.164 ; gain = 51.656 ; free physical = 21702 ; free virtual = 48466 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.594 ; gain = 64.086 ; free physical = 21688 ; free virtual = 48453 Phase 3 Initial Routing Writing bitstream ./design.bit... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.594 ; gain = 64.086 ; free physical = 21677 ; free virtual = 48444 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.594 ; gain = 64.086 ; free physical = 21675 ; free virtual = 48443 Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.594 ; gain = 64.086 ; free physical = 21674 ; free virtual = 48442 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.594 ; gain = 64.086 ; free physical = 21673 ; free virtual = 48442 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.594 ; gain = 64.086 ; free physical = 21673 ; free virtual = 48441 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.594 ; gain = 64.086 ; free physical = 21672 ; free virtual = 48441 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.594 ; gain = 64.086 ; free physical = 21723 ; free virtual = 48492 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.594 ; gain = 66.086 ; free physical = 21732 ; free virtual = 48501 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.594 ; gain = 67.086 ; free physical = 21792 ; free virtual = 48562 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2089.594 ; gain = 67.086 ; free physical = 21841 ; free virtual = 48610 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2128.383 ; gain = 137.891 ; free physical = 21846 ; free virtual = 48615 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing placer database... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2128.383 ; gain = 0.000 ; free physical = 21991 ; free virtual = 48765 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: 18d0b5f55 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2066.957 ; gain = 40.668 ; free physical = 21964 ; free virtual = 48735 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 18d0b5f55 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2073.945 ; gain = 47.656 ; free physical = 21920 ; free virtual = 48691 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 18d0b5f55 Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 2073.945 ; gain = 47.656 ; free physical = 21918 ; free virtual = 48689 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 21839 ; free virtual = 48610 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2086.250 ; gain = 59.961 ; free physical = 21834 ; free virtual = 48605 Phase 3 Initial Routing Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 21856 ; free virtual = 48627 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 21838 ; free virtual = 48610 Phase 4 Rip-up And Reroute | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 21838 ; free virtual = 48609 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 21840 ; free virtual = 48611 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 21839 ; free virtual = 48611 Phase 6 Post Hold Fix | Checksum: 18932909f Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 21837 ; free virtual = 48609 Phase 7 Route finalize ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2088.250 ; gain = 61.961 ; free physical = 21856 ; free virtual = 48628 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2090.250 ; gain = 63.961 ; free physical = 21854 ; free virtual = 48626 Phase 9 Depositing Routes INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10039 Phase 9 Depositing Routes | Checksum: 18932909f Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 21839 ; free virtual = 48612 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2091.250 ; gain = 64.961 ; free physical = 21873 ; free virtual = 48646 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:44 . Memory (MB): peak = 2130.039 ; gain = 135.766 ; free physical = 21874 ; free virtual = 48647 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2130.039 ; gain = 0.000 ; free physical = 21830 ; free virtual = 48606 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:07:39 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 2470.359 ; gain = 343.105 ; free physical = 21794 ; free virtual = 48568 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:07:39 2019... INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10088 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads touch build/specimen_012/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_014 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10199 Loading data files... INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10238 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 21998 ; free virtual = 48781 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 21886 ; free virtual = 48670 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 21867 ; free virtual = 48671 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1334.094 ; gain = 238.184 ; free physical = 21882 ; free virtual = 48666 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 21989 ; free virtual = 48773 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2] INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:1575] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/top.v:2] INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 21727 ; free virtual = 48514 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 21729 ; free virtual = 48516 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 21728 ; free virtual = 48516 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 21720 ; free virtual = 48508 INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 21536 ; free virtual = 48324 --------------------------------------------------------------------------------- Loading route data... Processing options... Creating bitmap... INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/top.v:2] ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 1338.062 ; gain = 242.152 ; free physical = 21423 ; free virtual = 48234 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 21442 ; free virtual = 48234 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1177.566 ; gain = 81.648 ; free physical = 21427 ; free virtual = 48237 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 21444 ; free virtual = 48237 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 21346 ; free virtual = 48157 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 21344 ; free virtual = 48156 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2062.180 ; gain = 43.668 ; free physical = 21338 ; free virtual = 48150 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 21337 ; free virtual = 48149 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Loading site data... Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2067.168 ; gain = 48.656 ; free physical = 21374 ; free virtual = 48187 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2067.168 ; gain = 48.656 ; free physical = 21373 ; free virtual = 48186 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading route data... Creating bitstream... Processing options... Creating bitmap... Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 2078.223 ; gain = 59.711 ; free physical = 21209 ; free virtual = 48021 Phase 3 Initial Routing --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 21225 ; free virtual = 48019 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 21224 ; free virtual = 48017 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 21198 ; free virtual = 47991 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 21199 ; free virtual = 47992 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 21198 ; free virtual = 47992 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 21198 ; free virtual = 47992 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 21196 ; free virtual = 47989 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 21195 ; free virtual = 47988 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2] INFO: Launching helper process for spawning children vivado processes Phase 7 Route finalize INFO: Helper process launched with PID 10324 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:504] Congestion Report North Dir 1x1 Area, Max Cong = WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:523] 0%, WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:528] No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. EastWARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:528] Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:672] Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2080.223 ; gain = 61.711 ; free physical = 21174 ; free virtual = 47968 Phase 8 Verifying routed nets WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:816] Verification completed successfully WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1200] Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.223 ; gain = 63.711 ; free physical = 21170 ; free virtual = 47964 WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 9 Depositing Routes WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1464] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.223 ; gain = 63.711 ; free physical = 21164 ; free virtual = 47958 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 2082.223 ; gain = 63.711 ; free physical = 21198 ; free virtual = 47992 Routing Is Done. 32 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:43 . Memory (MB): peak = 2121.012 ; gain = 134.516 ; free physical = 21199 ; free virtual = 47993 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.50 . Memory (MB): peak = 2121.012 ; gain = 0.000 ; free physical = 21135 ; free virtual = 47932 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 1342.094 ; gain = 246.184 ; free physical = 21041 ; free virtual = 47837 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1342.094 ; gain = 246.184 ; free physical = 21030 ; free virtual = 47827 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 21257 ; free virtual = 48059 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 21214 ; free virtual = 48016 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 21201 ; free virtual = 48003 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21175 ; free virtual = 47978 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 21076 ; free virtual = 47880 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21076 ; free virtual = 47879 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21074 ; free virtual = 47877 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21069 ; free virtual = 47873 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21068 ; free virtual = 47872 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21067 ; free virtual = 47870 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21065 ; free virtual = 47869 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21063 ; free virtual = 47867 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 21058 ; free virtual = 47862 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 21059 ; free virtual = 47862 --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 21053 ; free virtual = 47856 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 21038 ; free virtual = 47842 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 21032 ; free virtual = 47836 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 21022 ; free virtual = 47826 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 21014 ; free virtual = 47818 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 21014 ; free virtual = 47817 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 21010 ; free virtual = 47814 Synthesis Optimization Complete : Time (s): cpu = 00:00:35 ; elapsed = 00:00:41 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 21009 ; free virtual = 47813 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:08:02 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 2463.559 ; gain = 335.176 ; free physical = 20986 ; free virtual = 47791 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 1371.070 ; gain = 275.152 ; free physical = 20986 ; free virtual = 47791 --------------------------------------------------------------------------------- INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:08:02 2019... Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run INFO: [Project 1-570] Preparing netlist for logic optimization Creating bitstream... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_013/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_014 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Loading data files... INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/top.v:2] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 21814 ; free virtual = 48619 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 21834 ; free virtual = 48640 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21851 ; free virtual = 48656 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 1371.102 ; gain = 275.184 ; free physical = 21840 ; free virtual = 48663 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10497 --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:36 . Memory (MB): peak = 1371.102 ; gain = 275.184 ; free physical = 21833 ; free virtual = 48660 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21818 ; free virtual = 48645 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21817 ; free virtual = 48644 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21815 ; free virtual = 48642 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21814 ; free virtual = 48641 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21813 ; free virtual = 48640 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21812 ; free virtual = 48639 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21811 ; free virtual = 48638 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 21828 ; free virtual = 48636 --------------------------------------------------------------------------------- Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 21827 ; free virtual = 48635 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 21828 ; free virtual = 48636 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 21784 ; free virtual = 48597 --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-570] Preparing netlist for logic optimization 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 21930 ; free virtual = 48762 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:38 . Memory (MB): peak = 1379.078 ; gain = 283.160 ; free physical = 21989 ; free virtual = 48821 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1326.074 ; gain = 230.156 ; free physical = 22039 ; free virtual = 48852 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1334.102 ; gain = 238.184 ; free physical = 22038 ; free virtual = 48851 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 1379.078 ; gain = 283.160 ; free physical = 21956 ; free virtual = 48770 --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 1379.078 ; gain = 283.160 ; free physical = 21941 ; free virtual = 48755 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 21926 ; free virtual = 48740 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1462.719 ; gain = 0.000 ; free physical = 21925 ; free virtual = 48740 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:35 ; elapsed = 00:00:39 . Memory (MB): peak = 1379.078 ; gain = 283.160 ; free physical = 21912 ; free virtual = 48727 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1379.078 ; gain = 283.160 ; free physical = 21904 ; free virtual = 48718 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1379.078 ; gain = 283.160 ; free physical = 21894 ; free virtual = 48709 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1379.078 ; gain = 283.160 ; free physical = 21891 ; free virtual = 48706 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1379.078 ; gain = 283.160 ; free physical = 21889 ; free virtual = 48704 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1379.078 ; gain = 283.160 ; free physical = 21885 ; free virtual = 48700 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:39 . Memory (MB): peak = 1379.086 ; gain = 283.160 ; free physical = 21886 ; free virtual = 48701 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/top.v:2] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:27 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 21803 ; free virtual = 48634 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:08:09 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:30 . Memory (MB): peak = 2470.145 ; gain = 340.105 ; free physical = 21796 ; free virtual = 48633 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:08:09 2019... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:20 ; elapsed = 00:00:26 . Memory (MB): peak = 1325.074 ; gain = 229.156 ; free physical = 21824 ; free virtual = 48642 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:16] report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1461.715 ; gain = 0.000 ; free physical = 22748 ; free virtual = 49587 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1461.715 ; gain = 0.000 ; free physical = 22748 ; free virtual = 49587 touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_012 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:7] --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1325.074 ; gain = 229.156 ; free physical = 22632 ; free virtual = 49452 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1333.102 ; gain = 237.184 ; free physical = 22631 ; free virtual = 49451 --------------------------------------------------------------------------------- INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/top.v:2] INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 1336.070 ; gain = 240.152 ; free physical = 22652 ; free virtual = 49478 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 22616 ; free virtual = 49436 --------------------------------------------------------------------------------- Loading site data... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 22558 ; free virtual = 49381 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 22557 ; free virtual = 49380 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Loading route data... Processing options... Creating bitmap... INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 22394 ; free virtual = 49218 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1343.102 ; gain = 247.184 ; free physical = 22265 ; free virtual = 49091 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:21 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 22247 ; free virtual = 49074 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1343.102 ; gain = 247.184 ; free physical = 22238 ; free virtual = 49064 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2061.922 ; gain = 43.668 ; free physical = 22208 ; free virtual = 49034 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:90] Phase 2.1 Fix Topology Constraints WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:95] Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.910 ; gain = 49.656 ; free physical = 22151 ; free virtual = 48978 WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:100] Phase 2.2 Pre Route Cleanup WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:185] Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:185] Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.910 ; gain = 49.656 ; free physical = 22148 ; free virtual = 48974 WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2077.965 ; gain = 59.711 ; free physical = 22136 ; free virtual = 48964 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 22096 ; free virtual = 48923 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 22082 ; free virtual = 48910 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 22081 ; free virtual = 48909 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 22062 ; free virtual = 48890 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 22062 ; free virtual = 48890 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 22057 ; free virtual = 48886 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2079.965 ; gain = 61.711 ; free physical = 22031 ; free virtual = 48859 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2081.965 ; gain = 63.711 ; free physical = 22031 ; free virtual = 48859 Phase 9 Depositing Routes --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 1338.070 ; gain = 242.152 ; free physical = 22032 ; free virtual = 48860 --------------------------------------------------------------------------------- Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2081.965 ; gain = 63.711 ; free physical = 22029 ; free virtual = 48857 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:44 . Memory (MB): peak = 2081.965 ; gain = 63.711 ; free physical = 22064 ; free virtual = 48892 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2120.754 ; gain = 134.516 ; free physical = 22063 ; free virtual = 48891 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:40 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 22110 ; free virtual = 48939 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- Writing placer database... --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.43 . Memory (MB): peak = 2120.754 ; gain = 0.000 ; free physical = 22078 ; free virtual = 48909 --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Creating bitstream... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 21979 ; free virtual = 48810 --------------------------------------------------------------------------------- Running DRC as a precondition to command write_bitstream Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 21980 ; free virtual = 48811 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 21963 ; free virtual = 48794 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 21960 ; free virtual = 48791 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 21959 ; free virtual = 48790 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 21958 ; free virtual = 48788 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 21957 ; free virtual = 48788 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1351.078 ; gain = 255.160 ; free physical = 21955 ; free virtual = 48786 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:42 . Memory (MB): peak = 1351.086 ; gain = 255.160 ; free physical = 21957 ; free virtual = 48787 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-571] Translating synthesized netlist WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:16] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/top.v:2] WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 1345.102 ; gain = 249.184 ; free physical = 21963 ; free virtual = 48801 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 21942 ; free virtual = 48775 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Writing bitstream ./design.bit... --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 1345.102 ; gain = 249.184 ; free physical = 21894 ; free virtual = 48729 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 21929 ; free virtual = 48767 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:18 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 21932 ; free virtual = 48769 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 21971 ; free virtual = 48808 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 22050 ; free virtual = 48888 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 22109 ; free virtual = 48947 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:39 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 22060 ; free virtual = 48899 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21969 ; free virtual = 48809 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21959 ; free virtual = 48798 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Loading data files... --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21991 ; free virtual = 48830 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21989 ; free virtual = 48829 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21986 ; free virtual = 48826 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21986 ; free virtual = 48825 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21984 ; free virtual = 48824 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21956 ; free virtual = 48795 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 21955 ; free virtual = 48795 INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 21919 ; free virtual = 48759 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 21901 ; free virtual = 48741 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 21794 ; free virtual = 48634 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 21788 ; free virtual = 48628 --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 21776 ; free virtual = 48616 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 21845 ; free virtual = 48685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 21841 ; free virtual = 48681 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 21839 ; free virtual = 48679 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.078 ; gain = 257.160 ; free physical = 21836 ; free virtual = 48676 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:41 . Memory (MB): peak = 1353.086 ; gain = 257.160 ; free physical = 21836 ; free virtual = 48676 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:01:06 . Memory (MB): peak = 1476.820 ; gain = 393.938 ; free physical = 21823 ; free virtual = 48663 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1843.207 ; gain = 0.000 ; free physical = 21458 ; free virtual = 48299 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:08:27 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 42 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 2462.117 ; gain = 341.105 ; free physical = 21459 ; free virtual = 48300 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:08:27 2019... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 10852 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs touch build/specimen_010/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_015 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.250 ; gain = 468.531 ; free physical = 22422 ; free virtual = 49264 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.250 ; gain = 468.531 ; free physical = 22419 ; free virtual = 49261 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.250 ; gain = 468.531 ; free physical = 22417 ; free virtual = 49258 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.250 ; gain = 468.531 ; free physical = 22417 ; free virtual = 49258 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.250 ; gain = 468.531 ; free physical = 22416 ; free virtual = 49258 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1931.250 ; gain = 468.531 ; free physical = 22417 ; free virtual = 49258 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1931.250 ; gain = 533.562 ; free physical = 22417 ; free virtual = 49259 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1563.852 ; gain = 0.000 ; free physical = 22392 ; free virtual = 49234 INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.50 . Memory (MB): peak = 1563.852 ; gain = 0.000 ; free physical = 22339 ; free virtual = 49182 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 21763 ; free virtual = 48609 --------------------------------------------------------------------------------- INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 21754 ; free virtual = 48600 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 1344.555 ; gain = 248.938 ; free physical = 21746 ; free virtual = 48592 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21676 ; free virtual = 48523 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:05 . Memory (MB): peak = 1479.828 ; gain = 396.938 ; free physical = 21715 ; free virtual = 48562 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 21713 ; free virtual = 48560 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 21704 ; free virtual = 48551 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 21704 ; free virtual = 48551 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 21704 ; free virtual = 48551 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 21704 ; free virtual = 48551 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [DRC 23-27] Running DRC with 8 threads Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1932.246 ; gain = 470.531 ; free physical = 21706 ; free virtual = 48553 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 21706 ; free virtual = 48553 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Project 1-570] Preparing netlist for logic optimization Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21552 ; free virtual = 48400 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21552 ; free virtual = 48400 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21536 ; free virtual = 48384 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21533 ; free virtual = 48381 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21531 ; free virtual = 48379 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21531 ; free virtual = 48379 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21531 ; free virtual = 48379 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.578 ; gain = 269.961 ; free physical = 21531 ; free virtual = 48379 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 1365.586 ; gain = 269.961 ; free physical = 21532 ; free virtual = 48380 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-571] Translating synthesized netlist Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Loading site data... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11012 Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1552.859 ; gain = 0.000 ; free physical = 21413 ; free virtual = 48262 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.75 . Memory (MB): peak = 1552.859 ; gain = 0.000 ; free physical = 21371 ; free virtual = 48220 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 21375 ; free virtual = 48224 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-570] Preparing netlist for logic optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 21278 ; free virtual = 48128 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 21261 ; free virtual = 48112 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.57 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 21219 ; free virtual = 48070 INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:22] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:36] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 21118 ; free virtual = 47972 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 21101 ; free virtual = 47955 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 21100 ; free virtual = 47954 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 21093 ; free virtual = 47946 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 20997 ; free virtual = 47859 --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:09 . Memory (MB): peak = 1476.836 ; gain = 393.945 ; free physical = 21034 ; free virtual = 47896 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:41 . Memory (MB): peak = 1467.250 ; gain = 384.359 ; free physical = 21056 ; free virtual = 47918 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2] Phase 1.1 Placer Initialization Netlist Sorting WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 20778 ; free virtual = 47641 Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4148] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5642] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f Time (s): cpu = 00:00:00.30 ; elapsed = 00:00:00.37 . Memory (MB): peak = 1548.953 ; gain = 0.000 ; free physical = 20755 ; free virtual = 47619 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:592] Starting Placer Task WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/top.v:2] Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:08:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Phase 1 Placer Initialization 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:29 . Memory (MB): peak = 2459.859 ; gain = 339.105 ; free physical = 20622 ; free virtual = 47486 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:08:47 2019... Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1556.867 ; gain = 0.000 ; free physical = 20615 ; free virtual = 47480 No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 20664 ; free virtual = 47538 --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.38 ; elapsed = 00:00:00.43 . Memory (MB): peak = 1556.867 ; gain = 0.000 ; free physical = 20678 ; free virtual = 47552 --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 20709 ; free virtual = 47574 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1305.930 ; gain = 210.484 ; free physical = 20748 ; free virtual = 47614 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:21 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21593 ; free virtual = 48458 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Timing 38-35] Done setting XDC timing constraints. --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1211.949 ; gain = 116.500 ; free physical = 21576 ; free virtual = 48443 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 21575 ; free virtual = 48441 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 touch build/specimen_011/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_012 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:15 . Memory (MB): peak = 1219.977 ; gain = 124.527 ; free physical = 21528 ; free virtual = 48394 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21456 ; free virtual = 48323 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21452 ; free virtual = 48319 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21449 ; free virtual = 48315 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21448 ; free virtual = 48315 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21448 ; free virtual = 48314 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.340 ; gain = 0.000 ; free physical = 21447 ; free virtual = 48314 Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21447 ; free virtual = 48314 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21450 ; free virtual = 48316 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.906 ; gain = 218.461 ; free physical = 21448 ; free virtual = 48315 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.914 ; gain = 218.461 ; free physical = 21449 ; free virtual = 48316 INFO: [Project 1-571] Translating synthesized netlist Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:08 . Memory (MB): peak = 1476.836 ; gain = 393.945 ; free physical = 21430 ; free virtual = 48298 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.383 ; gain = 488.531 ; free physical = 21460 ; free virtual = 48328 Phase 1.3 Build Placer Netlist Model Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11293 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1554.867 ; gain = 0.000 ; free physical = 21094 ; free virtual = 47964 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.54 . Memory (MB): peak = 1554.867 ; gain = 0.000 ; free physical = 21001 ; free virtual = 47871 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1406.930 ; gain = 324.039 ; free physical = 20824 ; free virtual = 47695 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.383 ; gain = 488.531 ; free physical = 20812 ; free virtual = 47683 Phase 1.4 Constrain Clocks/Macros INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.383 ; gain = 488.531 ; free physical = 20788 ; free virtual = 47659 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.383 ; gain = 488.531 ; free physical = 20743 ; free virtual = 47614 Phase 2 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1967.348 ; gain = 0.000 ; free physical = 20722 ; free virtual = 47593 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.383 ; gain = 488.531 ; free physical = 20664 ; free virtual = 47535 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2052.383 ; gain = 488.531 ; free physical = 20581 ; free virtual = 47452 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.383 ; gain = 575.562 ; free physical = 20573 ; free virtual = 47445 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 20565 ; free virtual = 47437 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 20538 ; free virtual = 47411 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1472.961 ; gain = 0.000 ; free physical = 20523 ; free virtual = 47396 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1310.688 ; gain = 215.238 ; free physical = 20480 ; free virtual = 47353 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 20475 ; free virtual = 47348 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 20480 ; free virtual = 47353 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2055.391 ; gain = 502.531 ; free physical = 20483 ; free virtual = 47357 Phase 1.3 Build Placer Netlist Model --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 20462 ; free virtual = 47336 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 20462 ; free virtual = 47336 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 20460 ; free virtual = 47334 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 20460 ; free virtual = 47334 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 20460 ; free virtual = 47334 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 20460 ; free virtual = 47334 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 280| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 280| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 20459 ; free virtual = 47333 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 840 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.680 ; gain = 225.230 ; free physical = 20458 ; free virtual = 47332 Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 1320.688 ; gain = 225.230 ; free physical = 20459 ; free virtual = 47333 INFO: [Project 1-571] Translating synthesized netlist report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 20444 ; free virtual = 47319 Phase 1.3 Build Placer Netlist Model INFO: [Netlist 29-17] Analyzing 280 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2055.391 ; gain = 502.531 ; free physical = 20214 ; free virtual = 47090 Phase 1.4 Constrain Clocks/Macros --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 20213 ; free virtual = 47089 --------------------------------------------------------------------------------- Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2055.391 ; gain = 502.531 ; free physical = 20206 ; free virtual = 47083 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:28 . Memory (MB): peak = 2055.391 ; gain = 502.531 ; free physical = 20197 ; free virtual = 47074 Phase 2 Final Placement Cleanup Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 20182 ; free virtual = 47058 Phase 1.4 Constrain Clocks/Macros Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2055.391 ; gain = 502.531 ; free physical = 20174 ; free virtual = 47051 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 20182 ; free virtual = 47059 Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2055.391 ; gain = 502.531 ; free physical = 20180 ; free virtual = 47057 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2055.391 ; gain = 575.562 ; free physical = 20177 ; free virtual = 47054 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 20167 ; free virtual = 47045 Phase 2 Global Placement INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:70] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:75] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:110] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:130] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:130] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:135] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:140] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:145] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:150] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:150] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Phase 1 Build RT Design INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 15 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:32 . Memory (MB): peak = 1416.711 ; gain = 333.820 ; free physical = 19681 ; free virtual = 46560 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.441 ; gain = 0.000 ; free physical = 19530 ; free virtual = 46410 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19368 ; free virtual = 46249 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1484.742 ; gain = 0.000 ; free physical = 19351 ; free virtual = 46232 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a55af8d3 Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1484.742 ; gain = 0.000 ; free physical = 19346 ; free virtual = 46226 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19343 ; free virtual = 46224 Phase 3.2 Commit Most Macros & LUTRAMs INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19313 ; free virtual = 46194 Phase 3.3 Area Swap Optimization WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:16] Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19303 ; free virtual = 46184 Phase 3.4 Pipeline Register Optimization WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19299 ; free virtual = 46181 Phase 3.5 Small Shape Detail Placement INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_015/top.v:2] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 19288 ; free virtual = 46170 Phase 1.3 Build Placer Netlist Model Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1964.355 ; gain = 0.000 ; free physical = 19333 ; free virtual = 46218 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 19319 ; free virtual = 46202 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 19287 ; free virtual = 46171 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:17 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 19287 ; free virtual = 46170 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19206 ; free virtual = 46090 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19160 ; free virtual = 46044 Phase 3.7 Pipeline Register Optimization Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19132 ; free virtual = 46016 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19133 ; free virtual = 46018 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Phase 4 Post Placement Optimization and Clean-Up Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 19133 ; free virtual = 46017 Phase 1.3 Build Placer Netlist Model Phase 4.1 Post Commit Optimization Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19119 ; free virtual = 46003 Phase 4.2 Post Placement Cleanup INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 12227 Phase 1 Build RT Design | Checksum: 1307d6b8e Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2057.934 ; gain = 94.668 ; free physical = 19115 ; free virtual = 45999 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1307d6b8e Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2063.922 ; gain = 100.656 ; free physical = 19066 ; free virtual = 45951 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1307d6b8e Time (s): cpu = 00:00:39 ; elapsed = 00:00:42 . Memory (MB): peak = 2063.922 ; gain = 100.656 ; free physical = 19059 ; free virtual = 45944 Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19053 ; free virtual = 45937 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19041 ; free virtual = 45926 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:35 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 19013 ; free virtual = 45898 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 6d37d05e Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.977 ; gain = 107.711 ; free physical = 18966 ; free virtual = 45851 Phase 3 Initial Routing Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 18987 ; free virtual = 45872 Phase 1.4 Constrain Clocks/Macros Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18975 ; free virtual = 45860 Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 18951 ; free virtual = 45836 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.977 ; gain = 107.711 ; free physical = 18881 ; free virtual = 45766 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.977 ; gain = 107.711 ; free physical = 18860 ; free virtual = 45745 Phase 4 Rip-up And Reroute | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.977 ; gain = 107.711 ; free physical = 18860 ; free virtual = 45745 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.977 ; gain = 107.711 ; free physical = 18860 ; free virtual = 45745 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.977 ; gain = 107.711 ; free physical = 18860 ; free virtual = 45745 Phase 6 Post Hold Fix | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 2070.977 ; gain = 107.711 ; free physical = 18859 ; free virtual = 45745 Phase 7 Route finalize Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2003.156 ; gain = 454.203 ; free physical = 18838 ; free virtual = 45724 Phase 2 Global Placement Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2099.203 ; gain = 550.250 ; free physical = 18829 ; free virtual = 45715 Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 2099.203 ; gain = 631.953 ; free physical = 18821 ; free virtual = 45706 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = Running DRC as a precondition to command route_design 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 7 Route finalize | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.977 ; gain = 107.711 ; free physical = 18801 ; free virtual = 45686 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.977 ; gain = 110.711 ; free physical = 18792 ; free virtual = 45678 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 6d37d05e Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.977 ; gain = 110.711 ; free physical = 18788 ; free virtual = 45674 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.977 ; gain = 110.711 ; free physical = 18816 ; free virtual = 45701 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 2112.766 ; gain = 181.516 ; free physical = 18813 ; free virtual = 45699 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:20 . Memory (MB): peak = 1267.969 ; gain = 172.352 ; free physical = 18820 ; free virtual = 45705 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module top Detailed RTL Component Info : +---Registers : 8 Bit Registers := 2 +---Muxes : 2 Input 8 Bit Muxes := 1 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2112.766 ; gain = 0.000 ; free physical = 18801 ; free virtual = 45688 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.355 ; gain = 0.000 ; free physical = 18632 ; free virtual = 45519 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 133887d51 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2057.930 ; gain = 93.668 ; free physical = 18502 ; free virtual = 45390 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 133887d51 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2063.918 ; gain = 99.656 ; free physical = 18464 ; free virtual = 45352 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 133887d51 Time (s): cpu = 00:00:39 ; elapsed = 00:00:43 . Memory (MB): peak = 2063.918 ; gain = 99.656 ; free physical = 18464 ; free virtual = 45352 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 18349 ; free virtual = 45238 Phase 1.4 Constrain Clocks/Macros Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: f6c26eb9 Time (s): cpu = 00:00:39 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 18299 ; free virtual = 45187 Phase 3 Initial Routing Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:29 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 18236 ; free virtual = 45124 Phase 1 Placer Initialization | Checksum: 208e4f915 Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: f6c26eb9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 18164 ; free virtual = 45053 Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:30 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 18163 ; free virtual = 45052 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 18163 ; free virtual = 45052 Phase 2 Final Placement Cleanup Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: f6c26eb9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 18163 ; free virtual = 45052 Phase 4 Rip-up And Reroute | Checksum: f6c26eb9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 18162 ; free virtual = 45051 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: f6c26eb9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 18162 ; free virtual = 45051 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: f6c26eb9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 18162 ; free virtual = 45051 Phase 6 Post Hold Fix | Checksum: f6c26eb9 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 18162 ; free virtual = 45051 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 18198 ; free virtual = 45087 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2070.973 ; gain = 106.711 ; free physical = 18213 ; free virtual = 45102 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.973 ; gain = 109.711 ; free physical = 18213 ; free virtual = 45102 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: f6c26eb9 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.973 ; gain = 109.711 ; free physical = 18214 ; free virtual = 45103 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2073.973 ; gain = 109.711 ; free physical = 18248 ; free virtual = 45137 Routing Is Done. 28 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:46 . Memory (MB): peak = 2112.762 ; gain = 180.516 ; free physical = 18247 ; free virtual = 45136 Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 18246 ; free virtual = 45136 Phase 3.2 Commit Most Macros & LUTRAMs Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 495.531 ; free physical = 18230 ; free virtual = 45120 Writing placer database... Writing XDEF routing. 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.398 ; gain = 575.562 ; free physical = 18222 ; free virtual = 45113 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2112.762 ; gain = 0.000 ; free physical = 18220 ; free virtual = 45111 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:19 ; elapsed = 00:00:25 . Memory (MB): peak = 2052.398 ; gain = 497.531 ; free physical = 18185 ; free virtual = 45075 Phase 1.3 Build Placer Netlist Model Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:31 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 18161 ; free virtual = 45051 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1903.449 ; gain = 0.000 ; free physical = 18123 ; free virtual = 45013 Phase 3.3 Area Swap Optimization Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 18070 ; free virtual = 44960 Phase 3.4 Pipeline Register Optimization Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cd729a62 Time (s): cpu = 00:00:17 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 18071 ; free virtual = 44961 Phase 1.3 Build Placer Netlist Model Running DRC as a precondition to command write_bitstream Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 18076 ; free virtual = 44966 Phase 3.5 Small Shape Detail Placement Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 18091 ; free virtual = 44982 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 18089 ; free virtual = 44980 Phase 1 Placer Initialization | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 18084 ; free virtual = 44975 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: eaaa372b Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 18099 ; free virtual = 44989 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Ending Placer Task | Checksum: cd729a62 Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1991.492 ; gain = 518.531 ; free physical = 18115 ; free virtual = 45005 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1991.492 ; gain = 584.562 ; free physical = 18115 ; free virtual = 45005 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Loading data files... Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 18052 ; free virtual = 44944 --------------------------------------------------------------------------------- Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Time (s): cpu = 00:00:30 ; elapsed = 00:00:34 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 18065 ; free virtual = 44956 Phase 3.6 Re-assign LUT pins No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 1344.562 ; gain = 248.945 ; free physical = 18070 ; free virtual = 44962 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 18033 ; free virtual = 44925 Phase 3.7 Pipeline Register Optimization INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: cd729a62 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 17960 ; free virtual = 44852 --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:22 ; elapsed = 00:00:29 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 17947 ; free virtual = 44839 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 17953 ; free virtual = 44845 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.992 ; free physical = 17969 ; free virtual = 44861 --------------------------------------------------------------------------------- Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 17971 ; free virtual = 44863 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 17909 ; free virtual = 44801 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 17888 ; free virtual = 44780 Phase 4.4 Final Placement Cleanup Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 17873 ; free virtual = 44765 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 17853 ; free virtual = 44746 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 17851 ; free virtual = 44744 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 17833 ; free virtual = 44726 --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 17856 ; free virtual = 44748 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 17852 ; free virtual = 44745 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 17846 ; free virtual = 44738 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 17843 ; free virtual = 44735 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |top | din_shr_reg[7] | 8 | 1 | NO | YES | NO | 1 | 0 | +------------+----------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 6650| |3 |SRL16E | 1| |4 |FDRE | 9| |5 |IBUF | 3| |6 |OBUF | 1| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 6665| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 17840 ; free virtual = 44732 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 13302 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.586 ; gain = 269.969 ; free physical = 17834 ; free virtual = 44726 Synthesis Optimization Complete : Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 1365.594 ; gain = 269.969 ; free physical = 17834 ; free virtual = 44726 INFO: [Project 1-571] Translating synthesized netlist Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2091.199 ; gain = 542.246 ; free physical = 17822 ; free virtual = 44714 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:38 . Memory (MB): peak = 2091.199 ; gain = 623.949 ; free physical = 17824 ; free virtual = 44717 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 497.531 ; free physical = 17832 ; free virtual = 44725 Phase 1.4 Constrain Clocks/Macros INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 497.531 ; free physical = 17849 ; free virtual = 44742 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:23 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 497.531 ; free physical = 17794 ; free virtual = 44687 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:24 ; elapsed = 00:00:30 . Memory (MB): peak = 2052.398 ; gain = 497.531 ; free physical = 17755 ; free virtual = 44648 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:8] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:13] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:13] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:18] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:18] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:23] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:23] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:28] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:28] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:33] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:33] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:38] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:38] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:43] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:48] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:48] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:53] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:53] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:58] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:58] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:63] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:63] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:68] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:68] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:73] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:73] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:78] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:83] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:83] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:88] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:88] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:93] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:93] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:98] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:98] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:103] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:103] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:108] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:113] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:118] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:118] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:123] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:128] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:128] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:133] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:133] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:138] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:138] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:143] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:143] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:148] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:153] WARNING: [Synth 8-350] instance 'bram_RAMB18_X2Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:153] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:158] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:158] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:163] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:168] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:168] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:173] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:173] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:178] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:178] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:183] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:188] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:188] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:193] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:193] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:198] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:198] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:203] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:208] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:213] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:213] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:218] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:223] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:223] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:228] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:228] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:233] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:233] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:238] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:238] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:243] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:248] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:253] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:258] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:258] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:263] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:263] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:268] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:268] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:273] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:273] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:278] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:283] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:288] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:293] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:293] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:298] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:298] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:303] WARNING: [Synth 8-350] instance 'bram_RAMB18_X3Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:303] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:308] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:308] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:313] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:313] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:318] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y40' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:323] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y42' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:328] INFO: [Synth 8-638] synthesizing module 'RAMB18E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y44' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:333] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y46' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:333] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:338] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y48' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:338] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:343] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y50' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:343] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:348] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y52' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:348] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:353] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y54' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:353] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:358] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y56' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:363] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y58' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:363] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:368] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:373] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:373] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:378] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:378] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:383] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:383] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:388] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:388] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:393] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:398] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:398] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:403] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:408] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y20' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:408] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:413] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y22' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:418] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y24' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:418] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:423] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y26' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:423] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:428] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y28' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:433] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y30' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:433] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:438] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y32' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:438] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:443] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y34' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:443] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:448] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y36' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:453] WARNING: [Synth 8-350] instance 'bram_RAMB18_X4Y38' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:453] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:458] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y0' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:458] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:463] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y4' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:468] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y6' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:468] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:473] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y8' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:473] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:478] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y10' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:478] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:483] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y12' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:483] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:488] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y14' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:493] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y16' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:493] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:498] WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y18' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:503] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'bram_RAMB18_X0Y2' of module 'RAMB18E1' requires 22 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:503] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:24 ; elapsed = 00:00:31 . Memory (MB): peak = 2052.398 ; gain = 497.531 ; free physical = 17741 ; free virtual = 44635 INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/top.v:2] Loading data files... 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2052.398 ; gain = 575.562 ; free physical = 17742 ; free virtual = 44635 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 17760 ; free virtual = 44654 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 6653 Unisim elements for replacement --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1194.949 ; gain = 99.500 ; free physical = 17727 ; free virtual = 44622 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 17726 ; free virtual = 44621 --------------------------------------------------------------------------------- INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1202.977 ; gain = 107.527 ; free physical = 17710 ; free virtual = 44604 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design INFO: [Project 1-570] Preparing netlist for logic optimization report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1906.230 ; gain = 0.000 ; free physical = 16951 ; free virtual = 43849 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 509.531 ; free physical = 16838 ; free virtual = 43736 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 509.531 ; free physical = 16828 ; free virtual = 43726 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 509.531 ; free physical = 16822 ; free virtual = 43720 Phase 1 Placer Initialization | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 509.531 ; free physical = 16817 ; free virtual = 43716 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1652d5184 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 509.531 ; free physical = 16804 ; free virtual = 43703 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: a55af8d3 Time (s): cpu = 00:00:16 ; elapsed = 00:00:23 . Memory (MB): peak = 1994.273 ; gain = 509.531 ; free physical = 16805 ; free virtual = 43703 26 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 1994.273 ; gain = 577.562 ; free physical = 16805 ; free virtual = 43703 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Loading site data... Loading route data... Processing options... Creating bitmap... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: a55af8d3 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Creating bitstream... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Loading site data... 14 Infos, 203 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:44 . Memory (MB): peak = 1467.258 ; gain = 384.367 ; free physical = 16379 ; free virtual = 43282 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks Writing bitstream ./design.bit... INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Loading route data... Processing options... Creating bitmap... Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:25 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 16338 ; free virtual = 43245 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:25 . Memory (MB): peak = 1306.688 ; gain = 211.238 ; free physical = 16540 ; free virtual = 43448 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:25 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 16572 ; free virtual = 43480 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1542.961 ; gain = 0.000 ; free physical = 16525 ; free virtual = 43433 Creating bitstream... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 16523 ; free virtual = 43432 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 16523 ; free virtual = 43432 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 16522 ; free virtual = 43430 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 16521 ; free virtual = 43430 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 16520 ; free virtual = 43429 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d1abc39f --------------------------------------------------------------------------------- Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.47 . Memory (MB): peak = 1542.961 ; gain = 0.000 ; free physical = 16519 ; free virtual = 43427 Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 16518 ; free virtual = 43427 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |RAMB18E1 | 140| +------+---------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 140| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 16518 ; free virtual = 43427 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 280 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.664 ; gain = 219.215 ; free physical = 16517 ; free virtual = 43426 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:27 . Memory (MB): peak = 1314.672 ; gain = 219.215 ; free physical = 16519 ; free virtual = 43428 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 140 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:09:41 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Writing bitstream ./design.bit... 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2454.871 ; gain = 342.105 ; free physical = 16380 ; free virtual = 43291 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:09:41 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. touch build/specimen_014/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_016 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:34 . Memory (MB): peak = 1405.680 ; gain = 322.789 ; free physical = 17624 ; free virtual = 44542 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1 Build RT Design | Checksum: 1cc0cc705 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2137.066 ; gain = 52.668 ; free physical = 17619 ; free virtual = 44537 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1cc0cc705 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2146.055 ; gain = 61.656 ; free physical = 17574 ; free virtual = 44493 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1cc0cc705 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2146.055 ; gain = 61.656 ; free physical = 17575 ; free virtual = 44494 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_015/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:09:45 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 38 Infos, 33 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 2452.867 ; gain = 340.105 ; free physical = 17581 ; free virtual = 44500 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:09:45 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1469.711 ; gain = 0.000 ; free physical = 17703 ; free virtual = 44623 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2cf213e7 Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1469.711 ; gain = 0.000 ; free physical = 17853 ; free virtual = 44772 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Number of Nodes with overlaps = 0 touch build/specimen_015/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 Phase 2 Router Initialization | Checksum: 169be60b9 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 18505 ; free virtual = 45425 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 18457 ; free virtual = 45378 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 18456 ; free virtual = 45376 Phase 4 Rip-up And Reroute | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 18453 ; free virtual = 45373 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 18452 ; free virtual = 45372 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 18451 ; free virtual = 45371 Phase 6 Post Hold Fix | Checksum: 169be60b9 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 18448 ; free virtual = 45368 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 18434 ; free virtual = 45355 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 18433 ; free virtual = 45354 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 169be60b9 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 18480 ; free virtual = 45406 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.984 ; gain = 96.586 ; free physical = 18522 ; free virtual = 45449 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:52 . Memory (MB): peak = 2219.773 ; gain = 167.391 ; free physical = 18522 ; free virtual = 45449 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Phase 1 Build RT Design | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2138.074 ; gain = 50.668 ; free physical = 18451 ; free virtual = 45407 Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2219.773 ; gain = 0.000 ; free physical = 18448 ; free virtual = 45406 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2148.062 ; gain = 60.656 ; free physical = 18410 ; free virtual = 45369 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1ba972725 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2148.062 ; gain = 60.656 ; free physical = 18410 ; free virtual = 45369 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 1b0fd6471 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2182.992 ; gain = 95.586 ; free physical = 18380 ; free virtual = 45314 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2182.992 ; gain = 95.586 ; free physical = 18372 ; free virtual = 45306 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2182.992 ; gain = 95.586 ; free physical = 18398 ; free virtual = 45332 Phase 4 Rip-up And Reroute | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2182.992 ; gain = 95.586 ; free physical = 18398 ; free virtual = 45332 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2182.992 ; gain = 95.586 ; free physical = 18397 ; free virtual = 45332 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2182.992 ; gain = 95.586 ; free physical = 18396 ; free virtual = 45331 Phase 6 Post Hold Fix | Checksum: 1b0fd6471 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2182.992 ; gain = 95.586 ; free physical = 18396 ; free virtual = 45331 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 7 Route finalize | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2182.992 ; gain = 95.586 ; free physical = 18388 ; free virtual = 45323 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 2182.992 ; gain = 95.586 ; free physical = 18383 ; free virtual = 45318 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1b0fd6471 Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2182.992 ; gain = 95.586 ; free physical = 18310 ; free virtual = 45245 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2182.992 ; gain = 95.586 ; free physical = 18354 ; free virtual = 45289 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 2221.781 ; gain = 166.391 ; free physical = 18354 ; free virtual = 45289 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2221.781 ; gain = 0.000 ; free physical = 18069 ; free virtual = 45034 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2221.781 ; gain = 0.000 ; free physical = 17931 ; free virtual = 44873 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1905.449 ; gain = 0.000 ; free physical = 17894 ; free virtual = 44835 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [Place 30-574] Poor placement for routing between an IO pin and BUFG. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2128.961 ; gain = 29.758 ; free physical = 17720 ; free virtual = 44663 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.949 ; gain = 37.746 ; free physical = 17699 ; free virtual = 44642 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.949 ; gain = 37.746 ; free physical = 17699 ; free virtual = 44642 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 133440dd2 Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 2003.164 ; gain = 460.203 ; free physical = 17686 ; free virtual = 44630 Phase 1.3 Build Placer Netlist Model Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2156.004 ; gain = 56.801 ; free physical = 17677 ; free virtual = 44620 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.004 ; gain = 56.801 ; free physical = 17704 ; free virtual = 44648 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.004 ; gain = 56.801 ; free physical = 17711 ; free virtual = 44654 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.004 ; gain = 56.801 ; free physical = 17711 ; free virtual = 44654 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.004 ; gain = 56.801 ; free physical = 17711 ; free virtual = 44654 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.004 ; gain = 56.801 ; free physical = 17711 ; free virtual = 44654 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.004 ; gain = 56.801 ; free physical = 17711 ; free virtual = 44654 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.004 ; gain = 56.801 ; free physical = 17701 ; free virtual = 44644 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.004 ; gain = 56.801 ; free physical = 17699 ; free virtual = 44642 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.004 ; gain = 56.801 ; free physical = 17698 ; free virtual = 44642 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:43 ; elapsed = 00:00:47 . Memory (MB): peak = 2156.004 ; gain = 56.801 ; free physical = 17733 ; free virtual = 44676 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:50 . Memory (MB): peak = 2194.793 ; gain = 95.590 ; free physical = 17732 ; free virtual = 44676 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing placer database... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1 Build RT Design | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2067.176 ; gain = 43.668 ; free physical = 17304 ; free virtual = 44263 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2074.164 ; gain = 50.656 ; free physical = 17251 ; free virtual = 44211 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: f9126c41 Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 2074.164 ; gain = 50.656 ; free physical = 17248 ; free virtual = 44208 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1898.199 ; gain = 0.000 ; free physical = 17258 ; free virtual = 44219 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 13621 Phase 1.3 Build Placer Netlist Model | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.164 ; gain = 460.203 ; free physical = 17229 ; free virtual = 44191 Phase 1.4 Constrain Clocks/Macros Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.242 ; gain = 516.531 ; free physical = 17226 ; free virtual = 44188 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.242 ; gain = 516.531 ; free physical = 17217 ; free virtual = 44180 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 1986.242 ; gain = 516.531 ; free physical = 17211 ; free virtual = 44174 Phase 1 Placer Initialization | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.242 ; gain = 516.531 ; free physical = 17206 ; free virtual = 44168 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: bca60bcf Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.242 ; gain = 516.531 ; free physical = 17201 ; free virtual = 44164 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 2cf213e7 Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1986.242 ; gain = 516.531 ; free physical = 17194 ; free virtual = 44157 27 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1986.242 ; gain = 580.562 ; free physical = 17193 ; free virtual = 44156 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 1.4 Constrain Clocks/Macros | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:27 . Memory (MB): peak = 2003.164 ; gain = 460.203 ; free physical = 17210 ; free virtual = 44173 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 5700a6dd Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2086.594 ; gain = 63.086 ; free physical = 17207 ; free virtual = 44171 Phase 3 Initial Routing Phase 1 Placer Initialization | Checksum: 188a0da2a Time (s): cpu = 00:00:22 ; elapsed = 00:00:28 . Memory (MB): peak = 2003.164 ; gain = 460.203 ; free physical = 17199 ; free virtual = 44164 Phase 2 Global Placement Loading data files... Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2086.594 ; gain = 63.086 ; free physical = 17165 ; free virtual = 44131 Writing XDEF routing. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2086.594 ; gain = 63.086 ; free physical = 17163 ; free virtual = 44130 Writing XDEF routing logical nets. Phase 4 Rip-up And Reroute | Checksum: 5700a6dd Writing XDEF routing special nets. Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2086.594 ; gain = 63.086 ; free physical = 17163 ; free virtual = 44131 Phase 5 Delay and Skew Optimization Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2194.793 ; gain = 0.000 ; free physical = 17163 ; free virtual = 44131 Phase 5 Delay and Skew Optimization | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2086.594 ; gain = 63.086 ; free physical = 17162 ; free virtual = 44130 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2086.594 ; gain = 63.086 ; free physical = 17161 ; free virtual = 44129 Phase 6 Post Hold Fix | Checksum: 5700a6dd Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2086.594 ; gain = 63.086 ; free physical = 17160 ; free virtual = 44128 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2086.594 ; gain = 63.086 ; free physical = 17140 ; free virtual = 44109 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2088.594 ; gain = 65.086 ; free physical = 17138 ; free virtual = 44107 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 5700a6dd Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.594 ; gain = 66.086 ; free physical = 17174 ; free virtual = 44143 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2089.594 ; gain = 66.086 ; free physical = 17210 ; free virtual = 44179 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 2128.383 ; gain = 136.891 ; free physical = 17211 ; free virtual = 44180 WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1 Build RT Design | Checksum: 1b23f6d9e Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2135.082 ; gain = 50.668 ; free physical = 17225 ; free virtual = 44172 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2128.383 ; gain = 0.000 ; free physical = 17179 ; free virtual = 44131 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2.1 Fix Topology Constraints | Checksum: 1b23f6d9e Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2145.070 ; gain = 60.656 ; free physical = 17093 ; free virtual = 44041 Phase 2.2 Pre Route Cleanup INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 2.2 Pre Route Cleanup | Checksum: 1b23f6d9e Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2145.070 ; gain = 60.656 ; free physical = 17089 ; free virtual = 44037 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 2cf213e7 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Running DRC as a precondition to command write_bitstream Number of Nodes with overlaps = 0 Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 2 Router Initialization | Checksum: 1cdf75140 Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 17042 ; free virtual = 43990 Phase 3 Initial Routing WARNING: [Place 46-30] place_design is not in timing mode. Skip physical synthesis in placer ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 17043 ; free virtual = 43992 WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 17043 ; free virtual = 43992 Phase 4 Rip-up And Reroute | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 17041 ; free virtual = 43991 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 17040 ; free virtual = 43989 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 17039 ; free virtual = 43989 Phase 6 Post Hold Fix | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 17039 ; free virtual = 43989 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2127.961 ; gain = 36.762 ; free physical = 17014 ; free virtual = 43964 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 16976 ; free virtual = 43926 Phase 2.1 Fix Topology Constraints Phase 8 Verifying routed nets Verification completed successfully Phase 2.1 Fix Topology Constraints | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2133.949 ; gain = 42.750 ; free physical = 16966 ; free virtual = 43915 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 . Memory (MB): peak = 2133.949 ; gain = 42.750 ; free physical = 16966 ; free virtual = 43915 Phase 8 Verifying routed nets | Checksum: 1cdf75140 Time (s): cpu = 00:00:44 ; elapsed = 00:00:49 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 16957 ; free virtual = 43907 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 1cdf75140 Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 16958 ; free virtual = 43909 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:50 . Memory (MB): peak = 2180.000 ; gain = 95.586 ; free physical = 17015 ; free virtual = 43965 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:52 . Memory (MB): peak = 2218.789 ; gain = 166.391 ; free physical = 17016 ; free virtual = 43966 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 17003 ; free virtual = 43953 Phase 3 Initial Routing Phase 2 Global Placement | Checksum: 18079d4e9 Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 16997 ; free virtual = 43948 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X0Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X1Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X2Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y46: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y48: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y4: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y50: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y52: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y54: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y56: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y58: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y6: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X3Y8: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y0: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y10: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y12: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y14: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y16: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y18: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y20: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y22: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y24: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y26: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y28: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y2: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y30: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y32: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y34: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y36: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y38: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y40: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y42: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [DRC AVAL-4] enum_USE_DPORT_FALSE_enum_DREG_ADREG_0_connects_CED_CEAD_RSTD_GND: dsp_DSP48_X4Y44: DSP48E1 is not using the D port (USE_DPORT = FALSE). For improved power characteristics, set DREG and ADREG to '1', tie CED, CEAD, and RSTD to logic '0'. INFO: [Common 17-14] Message 'DRC AVAL-4' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X0Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X1Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X2Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y46: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y48: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y4: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y50: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y52: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y54: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y56: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y58: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y6: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X3Y8: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y0: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y10: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y12: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y14: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y16: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y18: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y20: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y22: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y24: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y26: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y28: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y2: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y30: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y32: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y34: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y36: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y38: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y40: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y42: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [DRC REQP-32] with_OPMODE_USE_MULT_NONE: dsp_DSP48_X4Y44: To save power with this DSP48E1 OPMODE input pin programming the USE_MULT attribute should be set to NONE. INFO: [Common 17-14] Message 'DRC REQP-32' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings, 220 Advisories INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing placer database... Phase 3.1 Commit Multi Column Macros | Checksum: 18079d4e9 Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 16958 ; free virtual = 43909 Phase 3.2 Commit Most Macros & LUTRAMs Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 16936 ; free virtual = 43888 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 16926 ; free virtual = 43878 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 16926 ; free virtual = 43879 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 16926 ; free virtual = 43879 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 16927 ; free virtual = 43879 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 16927 ; free virtual = 43880 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 16899 ; free virtual = 43854 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 16897 ; free virtual = 43852 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 16898 ; free virtual = 43852 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:45 . Memory (MB): peak = 2153.004 ; gain = 61.805 ; free physical = 16931 ; free virtual = 43885 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2191.793 ; gain = 100.594 ; free physical = 16930 ; free virtual = 43885 Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 25c5092fa Time (s): cpu = 00:00:28 ; elapsed = 00:00:33 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 16905 ; free virtual = 43862 Writing placer database... Phase 3.3 Area Swap Optimization WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Phase 3.3 Area Swap Optimization | Checksum: 23216312d Time (s): cpu = 00:00:29 ; elapsed = 00:00:33 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 16863 ; free virtual = 43828 Phase 3.4 Pipeline Register Optimization INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 3.4 Pipeline Register Optimization | Checksum: 27fe3d14a Time (s): cpu = 00:00:29 ; elapsed = 00:00:34 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 16809 ; free virtual = 43778 Phase 3.5 Small Shape Detail Placement INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14359 Loading data files... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Phase 1 Build RT Design | Checksum: e9c56990 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2136.082 ; gain = 51.668 ; free physical = 16603 ; free virtual = 43596 INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Phase 3.5 Small Shape Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 16621 ; free virtual = 43615 Phase 3.6 Re-assign LUT pins Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2218.789 ; gain = 0.000 ; free physical = 16598 ; free virtual = 43598 Phase 3.6 Re-assign LUT pins | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 16587 ; free virtual = 43587 Phase 3.7 Pipeline Register Optimization Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 3.7 Pipeline Register Optimization | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 16504 ; free virtual = 43507 Phase 2.1 Fix Topology Constraints | Checksum: e9c56990 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2146.070 ; gain = 61.656 ; free physical = 16484 ; free virtual = 43488 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: e9c56990 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2146.070 ; gain = 61.656 ; free physical = 16487 ; free virtual = 43491 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2191.793 ; gain = 0.000 ; free physical = 16487 ; free virtual = 43493 Loading data files... Phase 3 Detail Placement | Checksum: 181723f81 Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 16482 ; free virtual = 43488 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:10:14 2019... Phase 4.1 Post Commit Optimization | Checksum: 181723f81 Abnormal program termination (11) Please check '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_012/hs_err_pid9549.log' for details Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 16488 ; free virtual = 43466 Phase 4.2 Post Placement Cleanup ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_012/OK' failed GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 1B" bash ../fuzzaddr/generate.sh build/specimen_015 Phase 4.2 Post Placement Cleanup | Checksum: 181723f81 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 17484 ; free virtual = 44440 Phase 4.3 Placer Reporting INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 4.3 Placer Reporting | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 17427 ; free virtual = 44383 Phase 4.4 Final Placement Cleanup Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 16f7d8d1d Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 17416 ; free virtual = 44372 Phase 3 Initial Routing Phase 4.4 Final Placement Cleanup | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 17348 ; free virtual = 44303 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.438 ; gain = 54.996 ; free physical = 17276 ; free virtual = 44232 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 17260 ; free virtual = 44216 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 181723f81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 17260 ; free virtual = 44216 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 17289 ; free virtual = 44245 Phase 4 Rip-up And Reroute | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 17284 ; free virtual = 44240 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 17278 ; free virtual = 44234 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 17274 ; free virtual = 44230 Phase 6 Post Hold Fix | Checksum: 16f7d8d1d Time (s): cpu = 00:00:44 ; elapsed = 00:00:48 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 17267 ; free virtual = 44223 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 17296 ; free virtual = 44253 Phase 8 Verifying routed nets Verification completed successfully Ending Placer Task | Checksum: 14b04db87 Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2108.215 ; gain = 565.254 ; free physical = 17294 ; free virtual = 44251 24 Infos, 205 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2108.215 ; gain = 640.957 ; free physical = 17293 ; free virtual = 44249 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 8 Verifying routed nets | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 17292 ; free virtual = 44248 Phase 9 Depositing Routes INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads Phase 9 Depositing Routes | Checksum: 16f7d8d1d Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 17179 ; free virtual = 44136 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2179.000 ; gain = 94.586 ; free physical = 17209 ; free virtual = 44166 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:52 . Memory (MB): peak = 2217.789 ; gain = 165.391 ; free physical = 17208 ; free virtual = 44165 Writing placer database... Phase 1 Build RT Design | Checksum: 1412f7e16 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2067.957 ; gain = 41.668 ; free physical = 17064 ; free virtual = 44023 Loading site data... Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 1412f7e16 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 17003 ; free virtual = 43964 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 1412f7e16 Time (s): cpu = 00:00:40 ; elapsed = 00:00:44 . Memory (MB): peak = 2074.945 ; gain = 48.656 ; free physical = 17026 ; free virtual = 43986 Loading route data... Processing options... Creating bitmap... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:1575] Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2087.375 ; gain = 61.086 ; free physical = 16995 ; free virtual = 43961 Phase 3 Initial Routing INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_016/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 17013 ; free virtual = 43983 --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 17000 ; free virtual = 43970 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1190.945 ; gain = 95.504 ; free physical = 16999 ; free virtual = 43970 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 16998 ; free virtual = 43969 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 16998 ; free virtual = 43969 --------------------------------------------------------------------------------- Phase 4 Rip-up And Reroute | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 16998 ; free virtual = 43969 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 16998 ; free virtual = 43969 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:41 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 16997 ; free virtual = 43968 Phase 6 Post Hold Fix | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:46 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 16997 ; free virtual = 43968 Phase 7 Route finalize INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 1198.973 ; gain = 103.531 ; free physical = 16994 ; free virtual = 43966 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y106 clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2088.375 ; gain = 62.086 ; free physical = 17005 ; free virtual = 43976 Phase 8 Verifying routed nets Verification completed successfully INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 8 Verifying routed nets | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2090.375 ; gain = 64.086 ; free physical = 17000 ; free virtual = 43972 Phase 9 Depositing Routes Checksum: PlaceDB: 81518fae ConstDB: 0 ShapeSum: c9b34bd9 RouteDB: 0 Phase 1 Build RT Design Phase 9 Depositing Routes | Checksum: 18cd8a3d7 Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 16978 ; free virtual = 43951 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:47 . Memory (MB): peak = 2091.375 ; gain = 65.086 ; free physical = 17013 ; free virtual = 43986 Routing Is Done. 33 Infos, 300 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:49 . Memory (MB): peak = 2130.164 ; gain = 135.891 ; free physical = 17012 ; free virtual = 43985 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Write XDEF Complete: Time (s): cpu = 00:00:00.86 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2130.164 ; gain = 0.000 ; free physical = 16922 ; free virtual = 43903 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2217.789 ; gain = 0.000 ; free physical = 16819 ; free virtual = 43809 Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/design.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2217.789 ; gain = 0.000 ; free physical = 16688 ; free virtual = 43654 Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Loading data files... Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:08 ; elapsed = 00:00:13 . Memory (MB): peak = 1177.559 ; gain = 81.648 ; free physical = 16502 ; free virtual = 43469 --------------------------------------------------------------------------------- Loading site data... Loading route data... Processing options... Creating bitmap... Loading site data... Loading route data... Processing options... Creating bitmap... INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2] INFO: [Synth 8-638] synthesizing module 'LUT6_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] Parameter INIT bound to: 64'b0000000000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-256] done synthesizing module 'LUT6_L' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20729] INFO: [Synth 8-638] synthesizing module 'MUXF7_L' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] INFO: [Synth 8-256] done synthesizing module 'MUXF7_L' (2#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21749] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y0' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:19] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:24] INFO: [Synth 8-638] synthesizing module 'MUXF8' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] INFO: [Synth 8-256] done synthesizing module 'MUXF8' (3#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:21761] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y0' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:24] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y1' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:48] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y1' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:48] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y10' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:67] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:72] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y10' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:72] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y11' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:91] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:96] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y11' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:96] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y12' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y12' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:120] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y13' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:139] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:144] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y13' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:144] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y14' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:163] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:168] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y14' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:168] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y15' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:187] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:192] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y15' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:192] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y16' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:216] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y16' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:216] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y17' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y17' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:240] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y18' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:259] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:264] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y18' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:264] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y19' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:283] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y19' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:288] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y2' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:307] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:312] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y2' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:312] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y20' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:331] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:336] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y20' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:336] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y21' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y21' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:360] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y22' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:384] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y22' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:384] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y23' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:403] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:408] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y23' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:408] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y24' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:427] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:432] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y24' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:432] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y25' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:451] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y25' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:456] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y26' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y26' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:480] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y27' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:499] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:504] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y27' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:504] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y28' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:528] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y28' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:528] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y29' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:552] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y29' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:552] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y3' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:576] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y3' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:576] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y30' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:595] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:600] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y30' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:600] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y31' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:619] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y31' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:624] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y32' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:643] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:648] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y32' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:648] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y33' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:667] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:672] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y33' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:672] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y34' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:691] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:696] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y34' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:696] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y35' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:715] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:720] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y35' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:720] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y36' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:739] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:744] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y36' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:744] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y37' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:763] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:768] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y37' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:768] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y38' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:787] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:792] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y38' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:792] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y39' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:811] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:816] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y39' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:816] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y4' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:835] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:840] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y4' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:840] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y40' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:864] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y40' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:864] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y41' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:883] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:888] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y41' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:888] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y42' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:912] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y42' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:912] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y43' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:931] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:936] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y43' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:936] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y44' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:955] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:960] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y44' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:960] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y45' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:979] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:984] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y45' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:984] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y46' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1003] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1008] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y46' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1008] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y47' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1027] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1032] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y47' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1032] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y48' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1051] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1056] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y48' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1056] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y49' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1075] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y49' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1080] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y5' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1099] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1104] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y5' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1104] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y6' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1123] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1128] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y6' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1128] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y7' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1147] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1152] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y7' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1152] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y8' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1171] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1176] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y8' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1176] WARNING: [Synth 8-350] instance 'f7_SLICE_X12Y9' of module 'MUXF7_L' requires 4 connections, but only 2 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1200] WARNING: [Synth 8-350] instance 'f8_SLICE_X12Y9' of module 'MUXF8' requires 4 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1200] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1224] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1248] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1272] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1296] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1368] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1392] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1416] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1464] Loading site data... WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1536] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1560] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1584] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1608] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1632] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1656] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1704] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1728] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1752] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1800] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1848] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1872] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1896] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1920] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1944] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1968] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:1992] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2016] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2040] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2064] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2088] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2136] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2184] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2208] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2256] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2304] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2328] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2352] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2376] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2400] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. Loading data files... Loading route data... Processing options... Creating bitmap... Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Creating bitstream... No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:27 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 15794 ; free virtual = 42768 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:27 . Memory (MB): peak = 1302.684 ; gain = 207.242 ; free physical = 15786 ; free virtual = 42760 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:27 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 15783 ; free virtual = 42757 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Creating bitstream... --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 15691 ; free virtual = 42666 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 15691 ; free virtual = 42666 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 15691 ; free virtual = 42666 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 15691 ; free virtual = 42666 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 15691 ; free virtual = 42666 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 15691 ; free virtual = 42666 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 15691 ; free virtual = 42666 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1310.660 ; gain = 215.219 ; free physical = 15691 ; free virtual = 42666 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 1310.668 ; gain = 215.219 ; free physical = 15693 ; free virtual = 42668 INFO: [Project 1-571] Translating synthesized netlist Creating bitstream... WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y15 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y16 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y17 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y18 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y19 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y2 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y20 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y21 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y22 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y23 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y24 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y25 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y26 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y27 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y28 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y29 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y3 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y30 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y31 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y32 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y33 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y34 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y35 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y36 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y37 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y38 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y39 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y4 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y40 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y41 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y42 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y43 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y44 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y45 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y46 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y47 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y48 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y49 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y5 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y6 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y7 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y8 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X0Y9 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y0 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y1 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y10 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y100 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y101 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y102 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y103 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y104 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y105 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y106 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y107 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y108 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y109 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y11 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y110 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y111 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y112 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y113 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y114 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y115 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y116 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y117 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y118 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y119 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y12 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y120 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y121 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y122 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y123 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y124 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y125 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y126 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y127 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y128 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y129 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y13 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y130 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y131 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y132 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y133 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y134 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y135 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y136 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y137 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y138 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y139 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y14 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y140 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y141 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A1' of cell lut_rom_SLICE_X100Y142 is not included in the LUT equation: 'O6=0'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. INFO: [Common 17-14] Message 'DRC PDCN-1569' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Project 1-570] Preparing netlist for logic optimization Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 39901 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. Writing bitstream ./design.bit... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 1397.684 ; gain = 314.797 ; free physical = 16262 ; free virtual = 43253 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading site data... Creating bitstream... Loading data files... Loading route data... Processing options... Creating bitmap... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:10:40 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 246 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 2463.559 ; gain = 335.176 ; free physical = 16209 ; free virtual = 43201 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:10:40 2019... report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 16212 ; free virtual = 43204 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: fe5a20e8 Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1462.715 ; gain = 0.000 ; free physical = 16213 ; free virtual = 43205 Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_014/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_017 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_010/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:10:41 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:49 . Memory (MB): peak = 2607.934 ; gain = 388.160 ; free physical = 17086 ; free virtual = 44079 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:10:41 2019... Loading site data... INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:10:41 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2533.398 ; gain = 338.605 ; free physical = 17122 ; free virtual = 44114 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:10:41 2019... Loading route data... Processing options... Creating bitmap... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 Writing bitstream ./design.bit... DONE Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE Creating bitstream... touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_018 touch build/specimen_010/OK INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_019 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Writing bitstream ./design.bit... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-256] done synthesizing module 'top' (4#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_014/top.v:2] INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 14979 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_011/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:10:47 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:00:48 . Memory (MB): peak = 2606.941 ; gain = 385.160 ; free physical = 19644 ; free virtual = 46668 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:10:47 2019... Bitstream size: 4243411 bytes --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:21 ; elapsed = 00:00:36 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 20760 ; free virtual = 47765 --------------------------------------------------------------------------------- Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_011/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 0 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_020 Creating bitstream... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1326.066 ; gain = 230.156 ; free physical = 20738 ; free virtual = 47746 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:22 ; elapsed = 00:00:37 . Memory (MB): peak = 1334.094 ; gain = 238.184 ; free physical = 20737 ; free virtual = 47745 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_014/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:10:49 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 41 Infos, 207 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:35 . Memory (MB): peak = 2531.898 ; gain = 340.105 ; free physical = 20737 ; free virtual = 47745 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:10:49 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_014/OK GENERATE_ARGS="--oneval 1 --design params.csv --dword 0 --dframe 0" bash ../fuzzaddr/generate.sh build/specimen_016 Loading site data... Loading route data... Processing options... Creating bitmap... Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:31 ; elapsed = 00:00:43 . Memory (MB): peak = 1338.062 ; gain = 242.152 ; free physical = 21865 ; free virtual = 48883 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.445 ; gain = 54.996 ; free physical = 21811 ; free virtual = 48830 --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:10:56 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. 43 Infos, 301 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:40 ; elapsed = 00:00:36 . Memory (MB): peak = 2468.770 ; gain = 338.605 ; free physical = 21818 ; free virtual = 48837 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:10:56 2019... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE touch build/specimen_012/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_013 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:8] INFO: [Synth 8-638] synthesizing module 'DSP48E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000001 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:8] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:15] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:15] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:22] INFO: [Synth 8-638] synthesizing module 'DSP48E1__parameterized0' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] Parameter ACASCREG bound to: 1 - type: integer Parameter ADREG bound to: 1 - type: integer Parameter ALUMODEREG bound to: 1 - type: integer Parameter AREG bound to: 1 - type: integer Parameter AUTORESET_PATDET bound to: NO_RESET - type: string Parameter A_INPUT bound to: DIRECT - type: string Parameter BCASCREG bound to: 1 - type: integer Parameter BREG bound to: 1 - type: integer Parameter B_INPUT bound to: DIRECT - type: string Parameter CARRYINREG bound to: 1 - type: integer Parameter CARRYINSELREG bound to: 1 - type: integer Parameter CREG bound to: 1 - type: integer Parameter DREG bound to: 1 - type: integer Parameter INMODEREG bound to: 1 - type: integer Parameter IS_ALUMODE_INVERTED bound to: 4'b0000 Parameter IS_CARRYIN_INVERTED bound to: 1'b0 Parameter IS_CLK_INVERTED bound to: 1'b0 Parameter IS_INMODE_INVERTED bound to: 5'b00000 Parameter IS_OPMODE_INVERTED bound to: 7'b0000000 Parameter MASK bound to: 48'b000000000000000000000000000000000000000000000000 Parameter MREG bound to: 1 - type: integer Parameter OPMODEREG bound to: 1 - type: integer Parameter PATTERN bound to: 48'b000000000000000000000000000000000000000000000000 Parameter PREG bound to: 1 - type: integer Parameter SEL_MASK bound to: MASK - type: string Parameter SEL_PATTERN bound to: PATTERN - type: string Parameter USE_DPORT bound to: FALSE - type: string Parameter USE_MULT bound to: MULTIPLY - type: string Parameter USE_PATTERN_DETECT bound to: NO_PATDET - type: string Parameter USE_SIMD bound to: ONE48 - type: string INFO: [Synth 8-256] done synthesizing module 'DSP48E1__parameterized0' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:3428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:22] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:29] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:29] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:36] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:36] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:43] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:43] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:50] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:57] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:57] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:64] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:64] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:71] WARNING: [Synth 8-350] instance 'dsp_DSP48_X1Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:71] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:78] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:78] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:85] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:92] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:92] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:99] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:99] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:106] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:106] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:113] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:113] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:120] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:127] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:127] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:134] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:134] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:141] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:141] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:148] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:148] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:155] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:162] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:162] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:169] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:169] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:176] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:176] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:183] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:183] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:190] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:197] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:197] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:204] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:204] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:211] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:211] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:218] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:218] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:225] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:232] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:232] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:239] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:246] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:246] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:253] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:253] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:260] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:267] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:267] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:274] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:281] WARNING: [Synth 8-350] instance 'dsp_DSP48_X4Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:281] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:288] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:295] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:302] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:302] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:309] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:309] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:316] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:316] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:323] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:323] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:330] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:337] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:337] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:344] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:344] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:351] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:351] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:358] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:358] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:365] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:372] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:372] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:379] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:379] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:386] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:386] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:393] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:393] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:400] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:407] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:407] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:414] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:414] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:421] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:421] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:428] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:428] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:435] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:442] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:442] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:449] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:449] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:456] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:456] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:463] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:463] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:470] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:477] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:477] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:484] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:491] WARNING: [Synth 8-350] instance 'dsp_DSP48_X2Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:491] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:498] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y0' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:498] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:505] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y4' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:512] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y40' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:512] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:519] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y42' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:519] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:526] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y44' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:526] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:533] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y46' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:533] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:540] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y48' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:540] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:547] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y50' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:547] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:554] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y52' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:554] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:561] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y54' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:561] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:568] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y56' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:568] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:575] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y58' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:582] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y6' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:582] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:589] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y8' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:589] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:596] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y10' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:596] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:603] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y12' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:603] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:610] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y14' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:617] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y16' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:617] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:624] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y18' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:624] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:631] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y2' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:631] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:638] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y20' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:638] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:645] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y22' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:645] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:652] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y24' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:652] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:659] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y26' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:659] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:666] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y28' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:666] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:673] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y30' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:673] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:680] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y32' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:680] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:687] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y34' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:687] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:694] WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y36' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:694] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:701] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'dsp_DSP48_X3Y38' of module 'DSP48E1' requires 49 connections, but only 0 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:701] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp/build/specimen_015/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 22598 ; free virtual = 49620 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:47 . Memory (MB): peak = 1342.094 ; gain = 246.184 ; free physical = 22598 ; free virtual = 49620 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1190.953 ; gain = 95.504 ; free physical = 22588 ; free virtual = 49610 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 22588 ; free virtual = 49610 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 1198.980 ; gain = 103.531 ; free physical = 22579 ; free virtual = 49602 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:48 . Memory (MB): peak = 1342.094 ; gain = 246.184 ; free physical = 22570 ; free virtual = 49592 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:53 . Memory (MB): peak = 2061.926 ; gain = 43.668 ; free physical = 22380 ; free virtual = 49402 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:53 . Memory (MB): peak = 2067.914 ; gain = 49.656 ; free physical = 22311 ; free virtual = 49333 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 15e82b8af Time (s): cpu = 00:00:40 ; elapsed = 00:00:53 . Memory (MB): peak = 2067.914 ; gain = 49.656 ; free physical = 22310 ; free virtual = 49332 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 117ddc37d Time (s): cpu = 00:00:40 ; elapsed = 00:00:54 . Memory (MB): peak = 2077.969 ; gain = 59.711 ; free physical = 22183 ; free virtual = 49206 Phase 3 Initial Routing INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1844.203 ; gain = 0.000 ; free physical = 22181 ; free virtual = 49204 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:35 ; elapsed = 00:00:49 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 22180 ; free virtual = 49203 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 22175 ; free virtual = 49198 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 22173 ; free virtual = 49196 Phase 4 Rip-up And Reroute | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 22173 ; free virtual = 49196 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 22173 ; free virtual = 49196 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 22173 ; free virtual = 49196 Phase 6 Post Hold Fix | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 22172 ; free virtual = 49195 Phase 7 Route finalize --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Creating bitstream... Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2080.969 ; gain = 62.711 ; free physical = 22165 ; free virtual = 49188 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 117ddc37d Time (s): cpu = 00:00:41 ; elapsed = 00:00:54 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 22164 ; free virtual = 49188 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 117ddc37d Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 22163 ; free virtual = 49186 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:55 . Memory (MB): peak = 2082.969 ; gain = 64.711 ; free physical = 22196 ; free virtual = 49219 Routing Is Done. 34 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:44 ; elapsed = 00:00:56 . Memory (MB): peak = 2121.758 ; gain = 135.516 ; free physical = 22195 ; free virtual = 49218 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2121.758 ; gain = 0.000 ; free physical = 22171 ; free virtual = 49196 INFO: [Common 17-1381] The checkpoint '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/design.dcp' has been generated. Command: write_bitstream -force design.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 22145 ; free virtual = 49168 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 22141 ; free virtual = 49165 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 22141 ; free virtual = 49164 Phase 1 Placer Initialization | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 22140 ; free virtual = 49164 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 1d21143fb Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 22138 ; free virtual = 49162 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: fe5a20e8 Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1932.246 ; gain = 469.531 ; free physical = 22139 ; free virtual = 49163 21 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 1932.246 ; gain = 534.562 ; free physical = 22139 ; free virtual = 49163 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:51 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 22049 ; free virtual = 49073 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:51 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 22035 ; free virtual = 49060 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:51 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 22062 ; free virtual = 49086 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:51 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 22073 ; free virtual = 49097 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:51 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 22074 ; free virtual = 49099 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:51 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 22073 ; free virtual = 49098 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |LUT6_L | 6650| |2 |MUXF7_L | 6650| |3 |MUXF8 | 6650| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 19950| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:51 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 22072 ; free virtual = 49097 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 19950 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:36 ; elapsed = 00:00:51 . Memory (MB): peak = 1350.070 ; gain = 254.160 ; free physical = 22068 ; free virtual = 49093 Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:51 . Memory (MB): peak = 1350.078 ; gain = 254.160 ; free physical = 22057 ; free virtual = 49081 INFO: [Project 1-571] Translating synthesized netlist Running DRC as a precondition to command write_bitstream Command: report_drc (run_mandatory_drcs) for: bitstream_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: fe5a20e8 ConstDB: 0 ShapeSum: 0 RouteDB: 0 Phase 1 Build RT Design Writing bitstream ./design.bit... WARNING: [DRC ZPS7-1] PS7 block required: The PS7 cell must be used in this Zynq design in order to enable correct default configuration. report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Project 1-821] Please set project.enableDesignId to be 'true'. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Netlist 29-17] Analyzing 13300 Unisim elements for replacement ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15332 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 21936 ; free virtual = 48968 --------------------------------------------------------------------------------- Phase 1 Build RT Design | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2130.969 ; gain = 22.754 ; free physical = 21930 ; free virtual = 48962 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- Phase 2.1 Fix Topology Constraints --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1305.934 ; gain = 210.484 ; free physical = 21900 ; free virtual = 48932 Phase 2.1 Fix Topology Constraints | Checksum: efff5506 --------------------------------------------------------------------------------- Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2136.957 ; gain = 28.742 ; free physical = 21900 ; free virtual = 48932 Phase 2.2 Pre Route Cleanup Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Phase 2.2 Pre Route Cleanup | Checksum: efff5506 Time (s): cpu = 00:00:40 ; elapsed = 00:00:48 . Memory (MB): peak = 2136.957 ; gain = 28.742 ; free physical = 21900 ; free virtual = 48932 --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 21899 ; free virtual = 48931 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Loading data files... Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 14c07d67f Time (s): cpu = 00:00:41 ; elapsed = 00:00:48 . Memory (MB): peak = 2157.012 ; gain = 48.797 ; free physical = 21900 ; free virtual = 48933 Phase 3 Initial Routing INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int/build/specimen_013/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:11:07 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.012 ; gain = 48.797 ; free physical = 21913 ; free virtual = 48946 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.012 ; gain = 48.797 ; free physical = 21916 ; free virtual = 48949 Phase 4 Rip-up And Reroute | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.012 ; gain = 48.797 ; free physical = 21915 ; free virtual = 48948 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.012 ; gain = 48.797 ; free physical = 21922 ; free virtual = 48955 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.012 ; gain = 48.797 ; free physical = 21922 ; free virtual = 48956 Phase 6 Post Hold Fix | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.012 ; gain = 48.797 ; free physical = 21923 ; free virtual = 48956 INFO: Launching helper process for spawning children vivado processes 47 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:01:04 ; elapsed = 00:00:45 . Memory (MB): peak = 2608.949 ; gain = 391.160 ; free physical = 21927 ; free virtual = 48960 Phase 7 Route finalize INFO: Helper process launched with PID 15392 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:11:07 2019... Router Utilization Summary Global Vertical Routing Utilization = 0.00393497 % Global Horizontal Routing Utilization = 0.0040568 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 7.20721%, No Congested Regions. South Dir 1x1 Area, Max Cong = 2.7027%, No Congested Regions. East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions. West Dir 1x1 Area, Max Cong = 8.82353%, No Congested Regions. Phase 7 Route finalize | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.012 ; gain = 48.797 ; free physical = 21942 ; free virtual = 48974 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.012 ; gain = 48.797 ; free physical = 21945 ; free virtual = 48977 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 8a792087 Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.012 ; gain = 48.797 ; free physical = 21955 ; free virtual = 48986 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:49 . Memory (MB): peak = 2157.012 ; gain = 48.797 ; free physical = 21990 ; free virtual = 49021 Routing Is Done. 31 Infos, 206 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:46 ; elapsed = 00:00:52 . Memory (MB): peak = 2195.801 ; gain = 87.586 ; free physical = 21990 ; free virtual = 49021 --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 22010 ; free virtual = 49042 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 22020 ; free virtual = 49052 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 22022 ; free virtual = 49054 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 22022 ; free virtual = 49054 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 22022 ; free virtual = 49054 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 22023 ; free virtual = 49055 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |DSP48E1 | 110| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 110| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 22023 ; free virtual = 49055 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 220 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.910 ; gain = 218.461 ; free physical = 22028 ; free virtual = 49061 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 1313.918 ; gain = 218.461 ; free physical = 22034 ; free virtual = 49067 INFO: [Project 1-571] Translating synthesized netlist INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' Writing placer database... Bitstream size: 4243411 bytes Config size: 1060815 words Number of configuration frames: 9996 DONE INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15435 INFO: [Netlist 29-28] Unisim Transformation completed in 2 CPU seconds WARNING: [Netlist 29-101] Netlist 'top' is not ideal for floorplanning, since the cellview 'top' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. touch build/specimen_013/OK GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_014 INFO: [Netlist 29-17] Analyzing 110 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:11:10 2019... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_015/OK' failed GENERATE_ARGS="--oneval 0 --design params.csv --dword 1 --dframe 15" bash ../fuzzaddr/generate.sh build/specimen_015 ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # proc run {} { # create_project -force -part $::env(XRAY_PART) design design # read_verilog top.v # synth_design -top top # # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] # set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] # # set_property CFGBVS VCCO [current_design] # set_property CONFIG_VOLTAGE 3.3 [current_design] # set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] # # set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] # # place_design # route_design # # write_checkpoint -force design.dcp # write_bitstream -force design.bit # } # run Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15579 Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 16 Infos, 200 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 1406.934 ; gain = 324.039 ; free physical = 23402 ; free virtual = 50439 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15633 report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.965 ; gain = 0.000 ; free physical = 23319 ; free virtual = 50356 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cd729a62 Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.18 . Memory (MB): peak = 1471.965 ; gain = 0.000 ; free physical = 23315 ; free virtual = 50353 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 23278 ; free virtual = 50316 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Loading site data... Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 23079 ; free virtual = 50118 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_017/top.v:2] Loading route data... --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 23081 ; free virtual = 50121 --------------------------------------------------------------------------------- Processing options... Creating bitmap... --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 23047 ; free virtual = 50087 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 23046 ; free virtual = 50085 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 23024 ; free virtual = 50063 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1150.434 ; gain = 54.996 ; free physical = 22987 ; free virtual = 50028 --------------------------------------------------------------------------------- ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_019/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 22903 ; free virtual = 49944 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 22893 ; free virtual = 49935 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 22893 ; free virtual = 49935 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 22886 ; free virtual = 49927 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_018/top.v:2] Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:11 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 22844 ; free virtual = 49886 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.941 ; gain = 95.504 ; free physical = 22826 ; free virtual = 49868 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 22826 ; free virtual = 49868 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.969 ; gain = 103.531 ; free physical = 22786 ; free virtual = 49828 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15708 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1150.441 ; gain = 54.996 ; free physical = 22593 ; free virtual = 49637 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1156.441 ; gain = 60.824 ; free physical = 22568 ; free virtual = 49612 --------------------------------------------------------------------------------- Creating bitstream... INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:2] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:90] INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] Parameter ALMOST_EMPTY_VALUE bound to: 1 - type: integer Parameter ALMOST_FULL_VALUE bound to: 1 - type: integer Parameter ARRAY_MODE bound to: ARRAY_MODE_4_X_8 - type: string Parameter SYNCHRONOUS_MODE bound to: FALSE - type: string INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y8' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:189] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y9' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:189] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:288] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y10' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:288] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:387] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y11' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:387] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:486] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:486] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:585] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:585] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:684] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:684] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:783] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y4' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:783] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:882] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y5' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:882] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:981] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:981] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y6' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1080] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1179] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X1Y7' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1179] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1278] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y1' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1377] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y2' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1377] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1476] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y3' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1476] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1575] WARNING: [Synth 8-350] instance 'fifo_IN_FIFO_X0Y0' of module 'IN_FIFO' requires 29 connections, but only 10 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:1575] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int/build/specimen_020/top.v:2] --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 22356 ; free virtual = 49401 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1190.949 ; gain = 95.504 ; free physical = 22408 ; free virtual = 49453 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 22402 ; free virtual = 49447 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z020clg400-1 --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 1198.977 ; gain = 103.531 ; free physical = 22393 ; free virtual = 49437 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:2] Parameter DIN_N bound to: 8 - type: integer Parameter DOUT_N bound to: 8 - type: integer WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:25] INFO: [Synth 8-638] synthesizing module 'CARRY4' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] INFO: [Synth 8-256] done synthesizing module 'CARRY4' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:961] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:25] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:30] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:30] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:35] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:35] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:40] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:40] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:45] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:45] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:50] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:50] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:55] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:55] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:60] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y15' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:60] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:65] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y16' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:65] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:70] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y17' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:70] Report RTL Partitions: WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:75] +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y18' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:75] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:80] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y19' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:80] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:85] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y2' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:85] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:90] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y20' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:90] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:95] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y21' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:95] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:100] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y22' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:100] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:105] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y23' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:105] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:110] No constraint files found. WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y24' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:110] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:115] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y25' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:115] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:120] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y26' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:125] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y27' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:125] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:130] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y28' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:130] Start RTL Component Statistics WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:135] --------------------------------------------------------------------------------- Detailed RTL Component Info : WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y29' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:135] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:140] --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y3' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:140] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:145] Hierarchical RTL Component report --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y30' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:145] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:150] --------------------------------------------------------------------------------- WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y31' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:150] Start Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:155] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y32' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:155] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:160] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y33' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:165] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y34' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:165] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:170] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y35' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:170] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:175] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y36' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:175] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:180] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y37' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:180] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:185] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y38' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:185] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:190] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y39' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:190] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:195] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y4' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:200] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y40' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:200] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:205] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y41' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:205] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:210] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y42' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:210] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:215] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y43' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:215] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:220] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y44' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:220] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:225] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y45' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:225] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:230] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y46' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:230] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:235] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y47' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:240] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y48' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:240] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:245] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y49' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:245] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:250] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y5' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:250] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:255] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y6' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:255] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:260] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y7' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:260] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:265] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y8' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:265] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:270] WARNING: [Synth 8-350] instance 'carry4_SLICE_X24Y9' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:270] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:275] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y0' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:275] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:280] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y1' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:280] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:285] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y10' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:285] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:290] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y100' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:290] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:295] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y101' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:295] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:300] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y102' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:300] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:305] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y103' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:305] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:310] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y104' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:310] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:315] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y105' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:315] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:320] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y106' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:320] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:325] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y107' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:325] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:330] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y108' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:335] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y109' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:335] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:340] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y11' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:340] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:345] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y110' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:345] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:350] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y111' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:350] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:355] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y112' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:355] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:360] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y113' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:360] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:365] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y114' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:370] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y115' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:370] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:375] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y116' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:375] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:380] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y117' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:380] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:385] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y118' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:385] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:390] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y119' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:390] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:395] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y12' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:395] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:400] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y120' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:400] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:405] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y121' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:410] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y122' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:410] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:415] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y123' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:415] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:420] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y124' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:420] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:425] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y125' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:425] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:430] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y126' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:430] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:435] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y127' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:435] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:440] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y128' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:445] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y129' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:445] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:450] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y13' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:450] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:455] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y130' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:455] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:460] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y131' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:460] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:465] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y132' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:465] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:470] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y133' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:470] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:475] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y134' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:475] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:480] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y135' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:480] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:485] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y136' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:485] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:490] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y137' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:490] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:495] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y138' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:495] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:500] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y139' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:500] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:505] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y14' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:505] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:510] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y140' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:510] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:515] WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y141' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:515] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:520] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-350] instance 'carry4_SLICE_X28Y142' of module 'CARRY4' requires 6 connections, but only 1 given [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:520] INFO: [Common 17-14] Message 'Synth 8-350' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Project 1-111] Unisim Transformation Summary: A total of 13300 instances were transformed. LUT6_L => LUT6: 6650 instances MUXF7_L => MUXF7: 6650 instances 18 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:56 ; elapsed = 00:01:15 . Memory (MB): peak = 1476.820 ; gain = 393.938 ; free physical = 22347 ; free virtual = 49393 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 22333 ; free virtual = 49378 --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 22321 ; free virtual = 49366 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22347 ; free virtual = 49393 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Writing bitstream ./design.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22959 ; free virtual = 50009 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22958 ; free virtual = 50008 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22956 ; free virtual = 50006 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22955 ; free virtual = 50005 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22954 ; free virtual = 50005 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22954 ; free virtual = 50005 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22957 ; free virtual = 50007 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22956 ; free virtual = 50006 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 22957 ; free virtual = 50007 INFO: [Project 1-571] Translating synthesized netlist Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Starting Placer Task --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 22945 ; free virtual = 49996 --------------------------------------------------------------------------------- INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 22931 ; free virtual = 49982 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- Phase 1 Placer Initialization --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22925 ; free virtual = 49976 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1558.852 ; gain = 0.000 ; free physical = 22913 ; free virtual = 49964 INFO: [Project 1-570] Preparing netlist for logic optimization Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 110ed1b10 Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1558.852 ; gain = 0.000 ; free physical = 22901 ; free virtual = 49952 Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element din_reg was removed. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:16] No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.680 ; gain = 207.242 ; free physical = 22867 ; free virtual = 49918 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.680 ; gain = 207.242 ; free physical = 22859 ; free virtual = 49911 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22849 ; free virtual = 49901 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22832 ; free virtual = 49884 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22831 ; free virtual = 49882 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22830 ; free virtual = 49882 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22829 ; free virtual = 49880 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22828 ; free virtual = 49879 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22825 ; free virtual = 49877 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22825 ; free virtual = 49876 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22821 ; free virtual = 49873 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:21 . Memory (MB): peak = 1310.672 ; gain = 215.219 ; free physical = 22822 ; free virtual = 49873 WARNING: [Synth 8-3848] Net dout in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:7] INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb/build/specimen_016/top.v:2] INFO: [Project 1-571] Translating synthesized netlist --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 22838 ; free virtual = 49891 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- INFO: [Common 17-186] '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block/build/specimen_012/design/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 5 04:11:28 2019. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2017.2/doc/webtalk_introduction.html. Starting Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1151.441 ; gain = 55.992 ; free physical = 22838 ; free virtual = 49890 --------------------------------------------------------------------------------- 44 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:35 ; elapsed = 00:00:27 . Memory (MB): peak = 2460.863 ; gain = 339.105 ; free physical = 22851 ; free virtual = 49904 INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:11:28 2019... ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22918 ; free virtual = 49971 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22918 ; free virtual = 49972 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22920 ; free virtual = 49975 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22920 ; free virtual = 49976 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22919 ; free virtual = 49976 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22919 ; free virtual = 49977 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ |1 |IN_FIFO | 16| +------+--------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 16| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22923 ; free virtual = 49981 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 32 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.656 ; gain = 215.219 ; free physical = 22929 ; free virtual = 49987 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 22933 ; free virtual = 49991 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization Bitstream size: 4243411 bytes --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1227.949 ; gain = 132.332 ; free physical = 23772 ; free virtual = 50824 Config size: 1060815 words --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z020clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:16 . Memory (MB): peak = 1235.977 ; gain = 140.359 ; free physical = 23773 ; free virtual = 50825 --------------------------------------------------------------------------------- Number of configuration frames: 9996 DONE INFO: [Device 21-403] Loading part xc7z020clg400-1 touch build/specimen_012/OK /fast/FPGA/PRJXRAY/prjxray.git/build/tools/segmatch -o build/segbits_tilegrid.tdb $(find build -name "segdata_tilegrid.txt") Reading build/specimen_011/segdata_tilegrid.txt. Reading build/specimen_006/segdata_tilegrid.txt. Reading build/specimen_008/segdata_tilegrid.txt. Reading build/specimen_007/segdata_tilegrid.txt. Reading build/specimen_001/segdata_tilegrid.txt. Reading build/specimen_005/segdata_tilegrid.txt. Reading build/specimen_009/segdata_tilegrid.txt. Reading build/specimen_004/segdata_tilegrid.txt. Reading build/specimen_010/segdata_tilegrid.txt. Reading build/specimen_012/segdata_tilegrid.txt. Reading build/specimen_002/segdata_tilegrid.txt. Reading build/specimen_003/segdata_tilegrid.txt. #of segments: 12 #of bits: 21992 #of tags: 140 #of const0 tags: 0 #of const1 tags: 0 min #of candidates: 1 max #of candidates: 1 avg #of candidates: 1.000 make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_block' ****** Vivado v2017.2 (64-bit) **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017 **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source /fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/generate.tcl # source "$::env(XRAY_DIR)/utils/utils.tcl" ## proc route_via { net nodes {assert 1} } { ## # Route a simple source to dest net via one or more intermediate nodes ## # the nodes do not have have to be directly reachable from each other ## # net: net name string ## # nodes: list of node or wires strings? ## # Returns 1 on success (previously would silently failed with antenna nets) ## ## set net [get_nets $net] ## # fixed_route: list of nodes in the full route ## # Begins at implicit node ## set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] ## # Implicit end node. Route it at the end ## lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] ## ## puts "Routing net $net:" ## ## foreach to_node $nodes { ## # convert wire string to node object ## set to_node [get_nodes -of_objects [get_wires $to_node]] ## # Start at the last point ## set from_node [lindex $fixed_route end] ## # Make vivado do the hard work ## puts " set route \[find_routing_path -quiet -from $from_node -to $to_node\]" ## set route [find_routing_path -quiet -from $from_node -to $to_node] ## # TODO: check for this ## if {$route == ""} { ## # This can also happen if you try to route to a node already in the route ## if { [ lsearch $route $to_node ] >= 0 } { ## puts " WARNING: route_via loop. $to_node is already in the path, ignoring" ## } else { ## puts " $from_node -> $to_node: no route found - assuming direct PIP" ## lappend fixed_route $to_node ## } ## } { ## puts " $from_node -> $to_node: $route" ## set fixed_route [concat $fixed_route [lrange $route 1 end]] ## } ## set_property -quiet FIXED_ROUTE $fixed_route $net ## } ## ## # Earlier check should catch this now ## set status [get_property ROUTE_STATUS $net] ## if { $status != "ROUTED" } { ## puts " Failed to route net $net, status $status, route: $fixed_route" ## if { $assert } { ## error "Failed to route net" ## } ## return 0 ## } ## ## set_property -quiet FIXED_ROUTE $fixed_route $net ## puts "" ## return 1 ## } ## proc tile_wire_pairs {tile1 tile2} { ## set tile1 [get_tiles $tile1] ## set tile2 [get_tiles $tile2] ## ## foreach wire1 [lsort [get_wires -of_objects $tile1]] { ## set wire2 [get_wires -quiet -filter "TILE_NAME == $tile2" -of_objects [get_nodes -quiet -of_objects $wire1]] ## if {$wire2 != ""} {puts "$wire1 $wire2"} ## } ## } ## proc randsample_list {num lst} { ## set rlst {} ## for {set i 0} {$i<$num} {incr i} { ## set j [expr {int(rand()*[llength $lst])}] ## lappend rlst [lindex $lst $j] ## set lst [lreplace $lst $j $j] ## } ## return $rlst ## } ## proc randplace_pblock {num pblock} { ## set sites [randsample_list $num [get_sites -filter {SITE_TYPE == SLICEL || SITE_TYPE == SLICEM} -of_objects [get_pblocks $pblock]]] ## set cells [randsample_list $num [get_cells -hierarchical -filter "PBLOCK == [get_pblocks $pblock] && REF_NAME == LUT6"]] ## for {set i 0} {$i<$num} {incr i} { ## set site [lindex $sites $i] ## set cell [lindex $cells $i] ## set_property LOC $site $cell ## } ## } ## proc roi_tiles {} { ## return [get_tiles -filter "GRID_POINT_X >= $::env(XRAY_ROI_GRID_X1) && \ ## GRID_POINT_X < $::env(XRAY_ROI_GRID_X2) && \ ## GRID_POINT_Y >= $::env(XRAY_ROI_GRID_Y1) && \ ## GRID_POINT_Y < $::env(XRAY_ROI_GRID_Y2)"] ## } ## proc pblock_tiles {pblock} { ## set clb_tiles [get_tiles -of_objects [get_sites -of_objects [get_pblocks $pblock]]] ## set int_tiles [get_tiles [regsub -all {CLBL[LM]} $clb_tiles INT]] ## return [get_tiles "$clb_tiles $int_tiles"] ## } ## proc lintersect {lst1 lst2} { ## set rlst {} ## foreach el $lst1 { ## set idx [lsearch $lst2 $el] ## if {$idx >= 0} {lappend rlst $el} ## } ## return $rlst ## } ## proc putl {lst} { ## foreach line $lst {puts $line} ## } ## proc write_pip_txtdata {filename} { ## puts "FUZ([pwd]): Writing $filename." ## set fp [open $filename w] ## set nets [get_nets -hierarchical] ## set nnets [llength $nets] ## set neti 0 ## foreach net $nets { ## incr neti ## if {($neti % 100) == 0 } { ## puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)" ## } ## foreach pip [get_pips -of_objects $net] { ## set tile [get_tiles -of_objects $pip] ## set src_wire [get_wires -uphill -of_objects $pip] ## set dst_wire [get_wires -downhill -of_objects $pip] ## set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] ## set dir_prop [get_property IS_DIRECTIONAL $pip] ## puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" ## } ## } ## close $fp ## } ## proc generate_top {} { ## create_project -force -part $::env(XRAY_PART) design design ## read_verilog top.v ## synth_design -top top ## ## set_property CFGBVS VCCO [current_design] ## set_property CONFIG_VOLTAGE 3.3 [current_design] ## set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] ## ## place_design ## route_design ## ## write_checkpoint -force design.dcp ## write_bitstream -force design.bit ## } # generate_top INFO: [Project 1-570] Preparing netlist for logic optimization Command: synth_design -top top Starting synth_design Using part: xc7z020clg400-1 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020-clg400' INFO: [Synth 8-638] synthesizing module 'top' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2] INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020-clg400' WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:37] INFO: [Synth 8-638] synthesizing module 'RAMB18E1' [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] Parameter DOA_REG bound to: 0 - type: integer Parameter DOB_REG bound to: 0 - type: integer Parameter INITP_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INITP_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_00 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_01 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_02 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_03 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_04 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_05 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_06 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_07 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_08 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_09 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_0F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_10 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_11 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_12 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_13 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_14 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_15 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_16 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_17 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_18 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_19 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_1F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_20 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_21 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_22 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_23 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_24 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_25 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_26 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_27 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_28 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_29 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_2F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_30 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_31 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_32 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_33 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_34 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_35 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_36 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_37 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_38 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_39 bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3A bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3B bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3C bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3D bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3E bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_3F bound to: 256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Parameter INIT_A bound to: 18'b000000000000000000 Parameter INIT_B bound to: 18'b000000000000000000 Parameter INIT_FILE bound to: NONE - type: string Parameter IS_CLKARDCLK_INVERTED bound to: 1'b0 Parameter IS_CLKBWRCLK_INVERTED bound to: 1'b0 Parameter IS_ENARDEN_INVERTED bound to: 1'b0 Parameter IS_ENBWREN_INVERTED bound to: 1'b0 Parameter IS_RSTRAMARSTRAM_INVERTED bound to: 1'b0 Parameter IS_RSTRAMB_INVERTED bound to: 1'b0 Parameter IS_RSTREGARSTREG_INVERTED bound to: 1'b0 Parameter IS_RSTREGB_INVERTED bound to: 1'b0 Parameter RAM_MODE bound to: TDP - type: string Parameter RDADDR_COLLISION_HWCONFIG bound to: DELAYED_WRITE - type: string Parameter READ_WIDTH_A bound to: 0 - type: integer Parameter READ_WIDTH_B bound to: 0 - type: integer Parameter RSTREG_PRIORITY_A bound to: RSTREG - type: string Parameter RSTREG_PRIORITY_B bound to: RSTREG - type: string Parameter SIM_COLLISION_CHECK bound to: ALL - type: string Parameter SIM_DEVICE bound to: 7SERIES - type: string Parameter SRVAL_A bound to: 18'b000000000000000000 Parameter SRVAL_B bound to: 18'b000000000000000000 Parameter WRITE_MODE_A bound to: WRITE_FIRST - type: string Parameter WRITE_MODE_B bound to: WRITE_FIRST - type: string Parameter WRITE_WIDTH_A bound to: 0 - type: integer Parameter WRITE_WIDTH_B bound to: 0 - type: integer INFO: [Synth 8-256] done synthesizing module 'RAMB18E1' (1#1) [/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:41822] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:63] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:81] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:120] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:146] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:164] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:203] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:229] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:247] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:286] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:312] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:330] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:369] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:395] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:413] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:452] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:478] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:496] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:535] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:561] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:579] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:618] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:644] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:662] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:701] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:727] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:745] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:784] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:810] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:828] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:867] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:893] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:911] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:950] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:976] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:994] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1033] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1059] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1077] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1116] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1142] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1160] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1199] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1225] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1243] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1282] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1308] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1326] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1365] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1391] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1409] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1448] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1474] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1492] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1531] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1557] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1575] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1614] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1640] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1658] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1697] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1723] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1741] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1780] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1806] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1824] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1863] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1889] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1907] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1946] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1972] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1990] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2029] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2055] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2073] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2112] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2138] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2156] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2195] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2221] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2239] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2278] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2304] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2322] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2361] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2387] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2405] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2444] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2470] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2488] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2527] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2553] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2571] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2610] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2636] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2654] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2693] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2719] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2737] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2776] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2802] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2820] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2859] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2885] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2903] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2942] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2968] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2986] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3025] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3051] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3069] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3108] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3134] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3152] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3191] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3217] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3235] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3274] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3300] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3318] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3357] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3383] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3401] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3440] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3466] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3484] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3523] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3549] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3567] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3606] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3632] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3650] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3689] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3715] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3733] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3772] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3798] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3816] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3855] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3881] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3899] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3938] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3964] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:3982] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4021] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4047] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4065] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4104] WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4130] INFO: [Common 17-14] Message 'Synth 8-4446' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4148] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4231] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4314] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4397] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4480] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4563] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4646] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4729] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4812] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4895] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:4978] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5061] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5144] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5227] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5310] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5393] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5476] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5559] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5642] INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5725] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5808] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5891] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:5974] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6057] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6140] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6223] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6306] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6389] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6472] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6555] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6638] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6721] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6804] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6887] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6970] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7053] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7136] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7219] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7302] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7385] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7468] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7551] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7634] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7717] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7800] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7883] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7966] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8049] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8132] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8215] WARNING: [Synth 8-689] width (8) of port connection 'WEBWE' does not match port width (4) of module 'RAMB18E1' [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:8298] INFO: [Common 17-14] Message 'Synth 8-689' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. 10 Infos, 32 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:24 . Memory (MB): peak = 1397.688 ; gain = 314.797 ; free physical = 23465 ; free virtual = 50519 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Command: report_drc (run_mandatory_drcs) for: incr_eco_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design Command: report_drc (run_mandatory_drcs) for: placer_checks INFO: [DRC 23-27] Running DRC with 8 threads INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 15842 WARNING: [Synth 8-3848] Net RAMB18_X2Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:6] WARNING: [Synth 8-3848] Net RAMB18_X2Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:7] WARNING: [Synth 8-3848] Net RAMB18_X2Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:11] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:89] WARNING: [Synth 8-3848] Net RAMB18_X2Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:90] WARNING: [Synth 8-3848] Net RAMB18_X2Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:94] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:172] WARNING: [Synth 8-3848] Net RAMB18_X2Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:173] WARNING: [Synth 8-3848] Net RAMB18_X2Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:177] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:255] WARNING: [Synth 8-3848] Net RAMB18_X2Y42_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:256] WARNING: [Synth 8-3848] Net RAMB18_X2Y43_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:260] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:338] WARNING: [Synth 8-3848] Net RAMB18_X2Y44_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:339] WARNING: [Synth 8-3848] Net RAMB18_X2Y45_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:343] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:421] WARNING: [Synth 8-3848] Net RAMB18_X2Y46_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:422] WARNING: [Synth 8-3848] Net RAMB18_X2Y47_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:426] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:504] WARNING: [Synth 8-3848] Net RAMB18_X2Y48_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:505] WARNING: [Synth 8-3848] Net RAMB18_X2Y49_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:509] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:587] WARNING: [Synth 8-3848] Net RAMB18_X2Y50_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:588] WARNING: [Synth 8-3848] Net RAMB18_X2Y51_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:592] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:670] WARNING: [Synth 8-3848] Net RAMB18_X2Y52_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:671] WARNING: [Synth 8-3848] Net RAMB18_X2Y53_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:675] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:753] WARNING: [Synth 8-3848] Net RAMB18_X2Y54_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:754] WARNING: [Synth 8-3848] Net RAMB18_X2Y55_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:758] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:836] WARNING: [Synth 8-3848] Net RAMB18_X2Y56_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:837] WARNING: [Synth 8-3848] Net RAMB18_X2Y57_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:841] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:919] WARNING: [Synth 8-3848] Net RAMB18_X2Y58_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:920] WARNING: [Synth 8-3848] Net RAMB18_X2Y59_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:924] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1002] WARNING: [Synth 8-3848] Net RAMB18_X2Y6_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1003] WARNING: [Synth 8-3848] Net RAMB18_X2Y7_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1007] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1085] WARNING: [Synth 8-3848] Net RAMB18_X2Y8_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1086] WARNING: [Synth 8-3848] Net RAMB18_X2Y9_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1090] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1168] WARNING: [Synth 8-3848] Net RAMB18_X2Y10_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1169] WARNING: [Synth 8-3848] Net RAMB18_X2Y11_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1173] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1251] WARNING: [Synth 8-3848] Net RAMB18_X2Y12_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1252] WARNING: [Synth 8-3848] Net RAMB18_X2Y13_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1256] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1334] WARNING: [Synth 8-3848] Net RAMB18_X2Y14_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1335] WARNING: [Synth 8-3848] Net RAMB18_X2Y15_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1339] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1417] WARNING: [Synth 8-3848] Net RAMB18_X2Y16_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1418] WARNING: [Synth 8-3848] Net RAMB18_X2Y17_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1422] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1500] WARNING: [Synth 8-3848] Net RAMB18_X2Y18_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1501] WARNING: [Synth 8-3848] Net RAMB18_X2Y19_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1505] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1583] WARNING: [Synth 8-3848] Net RAMB18_X2Y2_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1584] WARNING: [Synth 8-3848] Net RAMB18_X2Y3_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1588] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1666] WARNING: [Synth 8-3848] Net RAMB18_X2Y20_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1667] WARNING: [Synth 8-3848] Net RAMB18_X2Y21_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1671] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1749] WARNING: [Synth 8-3848] Net RAMB18_X2Y22_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1750] WARNING: [Synth 8-3848] Net RAMB18_X2Y23_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1754] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1832] WARNING: [Synth 8-3848] Net RAMB18_X2Y24_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1833] WARNING: [Synth 8-3848] Net RAMB18_X2Y25_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1837] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1915] WARNING: [Synth 8-3848] Net RAMB18_X2Y26_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1916] WARNING: [Synth 8-3848] Net RAMB18_X2Y27_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1920] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1998] WARNING: [Synth 8-3848] Net RAMB18_X2Y28_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:1999] WARNING: [Synth 8-3848] Net RAMB18_X2Y29_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2003] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2081] WARNING: [Synth 8-3848] Net RAMB18_X2Y30_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2082] WARNING: [Synth 8-3848] Net RAMB18_X2Y31_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2086] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2164] WARNING: [Synth 8-3848] Net RAMB18_X2Y32_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2165] WARNING: [Synth 8-3848] Net RAMB18_X2Y33_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2169] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2247] WARNING: [Synth 8-3848] Net RAMB18_X2Y34_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2248] WARNING: [Synth 8-3848] Net RAMB18_X2Y35_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2252] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2330] WARNING: [Synth 8-3848] Net RAMB18_X2Y36_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2331] WARNING: [Synth 8-3848] Net RAMB18_X2Y37_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2335] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2413] WARNING: [Synth 8-3848] Net RAMB18_X2Y38_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2414] WARNING: [Synth 8-3848] Net RAMB18_X2Y39_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2418] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2496] WARNING: [Synth 8-3848] Net RAMB18_X3Y0_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2497] WARNING: [Synth 8-3848] Net RAMB18_X3Y1_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2501] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2579] WARNING: [Synth 8-3848] Net RAMB18_X3Y4_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2580] WARNING: [Synth 8-3848] Net RAMB18_X3Y5_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2584] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2662] WARNING: [Synth 8-3848] Net RAMB18_X3Y40_wraddr in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2663] WARNING: [Synth 8-3848] Net RAMB18_X3Y41_webwe in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2667] WARNING: [Synth 8-3848] Net RAMB18_X3Y42_dibdi in module/entity top does not have driver. [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2745] INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-256] done synthesizing module 'top' (2#1) [/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/top.v:2] An unrecoverable error has occurred, synthesis cancelled. An unrecoverable error has occurred, synthesis cancelled. Part Resources: DSPs: 220 (col length:60) BRAMs: 280 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Abnormal program termination (6) Please check '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int/build/specimen_013/hs_err_pid15247.log' for details ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_013/OK' failed No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 23629 ; free virtual = 50691 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1302.688 ; gain = 207.242 ; free physical = 23614 ; free virtual = 50677 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 1310.664 ; gain = 215.219 ; free physical = 23597 ; free virtual = 50660 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--../fuzzaddr/common.mk:12: recipe for target 'build/specimen_016/OK' failed An unrecoverable error has occurred, synthesis cancelled. An unrecoverable error has occurred, synthesis cancelled. ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_014/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/bram_int' Makefile:84: recipe for target 'bram_int/build/segbits_tilegrid.tdb' failed INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1964.340 ; gain = 0.000 ; free physical = 24117 ; free virtual = 51189 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 110ed1b10 Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 2052.383 ; gain = 493.531 ; free physical = 23960 ; free virtual = 51033 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 208e4f915 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 2052.383 ; gain = 493.531 ; free physical = 23117 ; free virtual = 50192 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 208e4f915 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 2052.383 ; gain = 493.531 ; free physical = 23106 ; free virtual = 50181 Phase 1 Placer Initialization | Checksum: 208e4f915 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 2052.383 ; gain = 493.531 ; free physical = 23106 ; free virtual = 50181 Phase 2 Final Placement Cleanup Phase 2 Final Placement Cleanup | Checksum: 208e4f915 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 2052.383 ; gain = 493.531 ; free physical = 23104 ; free virtual = 50179 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: 110ed1b10 Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 2052.383 ; gain = 493.531 ; free physical = 23121 ; free virtual = 50196 29 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 2052.383 ; gain = 575.562 ; free physical = 23121 ; free virtual = 50196 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z020-clg400' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020-clg400' Running DRC as a precondition to command route_design Command: report_drc (run_mandatory_drcs) for: router_checks INFO: [DRC 23-27] Running DRC with 8 threads report_drc (run_mandatory_drcs) completed successfully INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Checksum: PlaceDB: 9a0637a8 ConstDB: 0 ShapeSum: 76e6e368 RouteDB: 0 Phase 1 Build RT Design ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_015/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/dsp' Makefile:87: recipe for target 'dsp/build/segbits_tilegrid.tdb' failed ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_017/OK' failed Phase 1 Build RT Design | Checksum: 118b3be9c Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 2135.066 ; gain = 50.668 ; free physical = 23968 ; free virtual = 51061 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 118b3be9c Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 2144.055 ; gain = 59.656 ; free physical = 24812 ; free virtual = 51906 Phase 2.2 Pre Route Cleanup ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_018/OK' failed Phase 2.2 Pre Route Cleanup | Checksum: 118b3be9c Time (s): cpu = 00:00:30 ; elapsed = 00:00:24 . Memory (MB): peak = 2144.055 ; gain = 59.656 ; free physical = 24849 ; free virtual = 51942 Number of Nodes with overlaps = 0 ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_019/OK' failed Phase 2 Router Initialization | Checksum: 145a2d7e1 Time (s): cpu = 00:00:30 ; elapsed = 00:00:24 . Memory (MB): peak = 2179.984 ; gain = 95.586 ; free physical = 25820 ; free virtual = 52914 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: 145a2d7e1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2179.984 ; gain = 95.586 ; free physical = 25824 ; free virtual = 52917 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: 145a2d7e1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2179.984 ; gain = 95.586 ; free physical = 25824 ; free virtual = 52917 Phase 4 Rip-up And Reroute | Checksum: 145a2d7e1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2179.984 ; gain = 95.586 ; free physical = 25824 ; free virtual = 52917 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: 145a2d7e1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2179.984 ; gain = 95.586 ; free physical = 25824 ; free virtual = 52917 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: 145a2d7e1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2179.984 ; gain = 95.586 ; free physical = 25824 ; free virtual = 52917 Phase 6 Post Hold Fix | Checksum: 145a2d7e1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2179.984 ; gain = 95.586 ; free physical = 25824 ; free virtual = 52917 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. Phase 7 Route finalize | Checksum: 145a2d7e1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2179.984 ; gain = 95.586 ; free physical = 25824 ; free virtual = 52917 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 145a2d7e1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 2179.984 ; gain = 95.586 ; free physical = 25825 ; free virtual = 52919 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 145a2d7e1 Time (s): cpu = 00:00:32 ; elapsed = 00:00:24 . Memory (MB): peak = 2179.984 ; gain = 95.586 ; free physical = 25826 ; free virtual = 52920 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:32 ; elapsed = 00:00:24 . Memory (MB): peak = 2179.984 ; gain = 95.586 ; free physical = 25869 ; free virtual = 52963 Routing Is Done. 36 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:26 . Memory (MB): peak = 2218.773 ; gain = 166.391 ; free physical = 25869 ; free virtual = 52963 Writing placer database... ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_020/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/fifo_int' Makefile:93: recipe for target 'fifo_int/build/segbits_tilegrid.tdb' failed INFO: [Common 17-206] Exiting Vivado at Tue Mar 5 04:12:15 2019... ../fuzzaddr/common.mk:12: recipe for target 'build/specimen_014/OK' failed make[3]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid/clb_int' Makefile:54: recipe for target 'clb_int/build/segbits_tilegrid.tdb' failed make[2]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid' Makefile:116: recipe for target 'run' failed make[1]: Leaving directory '/fast/FPGA/PRJXRAY/prjxray.git/fuzzers/005-tilegrid'